Page 306 - ARM 64 Bit Assembly Language

Floating point 295

Figure 9.2: With the FP/NEON instructions, parts of register Vn can be accessed by using
different views. Each view has a unique name.

d31, or as thirty-two single-word (32 bit) registers, named s0 through s31. Each register can
also be referred to as a halfword register (h0 through h31) or a byte register (b0 through b31).
Additionally, portions of each register can be referred to by using a subscript notation, such as
v1.f64[1] which refers to the upper 64 bits of register v1.

The processor supports IEEE single precision and double precision numbers. Each of the first
sixteen double precision registers can be used to store either one 64-bit number or two 32-bit
numbers. For example, double precision register d0 mayalsobereferredtoassingleprecision
registers s0 and s1. Registers d16 through d31 cannot be used as single precision registers
using the basic FP instructions.

The VFP instruction set added about 28 new instructions to the ARM instruction set. The
exact number of VFP instructions depended on the specific version of the VFP coproces-
sor. AArch64 supports instructions equivalent to the VFPv4 instruction set. There 23 basic
instructions in the AArch64 FP/NEON instruction set, but some have several variations. In-
structions are provided to:

• transfer floating point values between FP registers,
• transfer floating-point values between the FP coprocessor registers and main mem-
ory,
• transfer 32-bit values between the FP coprocessor registers and the ARM integer regis-
ters,
• perform addition, subtraction, multiplication, and division, involving two source registers
and a destination register,
• compute the square root of a value,
• perform combined multiply-accumulate operations,
• perform conversions between various integer, fixed point, and floating point representa-
tions, and
• compare floating-point values.