Page 311 - ARM 64 Bit Assembly Language

300 Chapter 9

9.4.1.3 Examples

1 ldr s5,[x0] // load s5 from address in x0
2 str d4,[x3],#8 // store d4 using address in
3 // x3, then add 8 to x3
4 str s0,[x1,#4]! // Add 4 to x1, then load s0 from
5 // the resulting address

9.4.2 Load/store single register with unscaled offset

These versions of the single register load/store instructions allow moving data between mem-
ory and an FP/NEON register. These instructions can load/store a byte, half-word, word
(single precision), double-word (double precision), or a quad-word. These instructions use an
unscaled 9-bit offset. The following instructions are used to load or store a single FP/NEON
register:

ldur Load FP/NEON Register, and
stur Store FP/NEON Register.

9.4.2.1 Syntax

<op> Bt, <addr>
<op> Ht, <addr>
<op> St, <addr>
<op> Dt, <addr>
<op> Qt, <addr>

• <op> is either ldur or stur.
• <addr> is register-offset. The offset is not scaled by the size of the data.

9.4.2.2 Operations

Name Effect Description
ldur Yt ← Mem[addr] Load Yt,where Yt is any FP register.
stur Mem[addr] ← Yt Store Yt,where Yt is any FP register.

9.4.2.3 Examples

1 ldur s5,[x0] // load s5 from address in x0
2 stur d4,[x3],#8 // store d4 using address in
3 // x3, then add 8 to x3