Page 305 - ARM 64 Bit Assembly Language
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294 Chapter 9
Figure 9.1: AArch64 Integer (left) and FP/NEON (right) User Program Registers.
Fig. 9.1 shows the 32 AArch64 integer registers, and the additional registers provided by the
AArch64 Advanced SIMD instruction set. As shown in Fig. 9.2, AArch64 FP/NEON instruc-
tions provide the ability to view the register set as thirty-two quadruple-word (128 bit) regis-
ters, named q0 through q31, or thirty-two double word (64 bit) registers, named d0 through
