Page 349 - Analog and Digital Filter Design

346 Analog and Digital Filter Design

to the second latch’s input. After the second clock cycle the second latch switches
its output to logic 1. Thus, if there are ten latches, all the Q outputs will be set
to logic 1 after ten clock cycles.

The secret of the Walking Ring’s operation is to loop the last output back to
the first input and to use a not-Q output somewhere in the chain to invert the
data sequence. The sequence of operations for Circuit A in Figure 14.5 follows.
Upon reset, the not-Q output is high. If this condition is input to a second latch
its output will go high after a clock cycle and each subsequent clock cycle will
cause an additional latch output to be set. This process will continue until all
the latches are set and the not-Q output that was used to set the first latch resets
to logic 0. Further clock cycles then cause subsequent latches to reset and return
to the initial condition from where the whole process begins again.

Circuit B in Figure 14.5 uses a CMOS CD4018 that has five latches connected
in a chain, but all the outputs are inverting. The operation of circuit B can be
analyzed in a similar way to Circuit A, the sequence of operations follows here.
When the latches are reset at the start of operation outputs 6, 7, 8, 9, and 10
are all at logic 1. The other latch outputs are at logic 0, and so the synthesizer
output will be just above midrail potential. The next few clock cycles will cause
latch outputs 1, 2, 3, and 4 to be set to logic 1, the final cycle causing the syn-
thesizer output to equal the supply voltage.

The next clock cycle does not change the output potential but causes the delay
latch to output a logic 1 condition. Subsequent clock cycles reset latch outputs
6, 7, 8, 9, and 10 to logic 0, since they are inverted, and the synthesizer output
voltage falls with each cycle. The next four clock cycles causes latch outputs 1,
2,3, and 4 to be reset in turn. The synthesizer output is now equal to the ground
potential. This does not change with the next clock cycle, because the delay latch
just resets its output to logic 0 at this time. The next five clock cycles cause latch
outputs 6, 7, 8, 9, and 10 to be set to logic 1, which is back to the beginning of
the cycle.

Note that for an even number of latches there will be an odd number of resis-
tors because one of the latch outputs has no resistor connected. The latch with
no resistor provides a delay, so that the output voltage will remain at the supply
voltage or ground for two clock cycles. The double clock period at either supply
rail ensures that the maximum output is available when the signal is filtered.
Resistor R1 provides the first step output, which is also the smallest and there-
fore has the highest resistance (since the step size is proportional to the current).
Resistor R1 is connected to the first latch that follows the delay latch, and this
is also the first output after the inversion of the latch outputs.