Page 125 - Bebop to The Boolean Boogie An Unconventional Guide to Electronics Fundamentals, Components, and Processes
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106 rn Chapter Eleven
Consider the circuit fragments shown in Figure 11-1. Each of these
fragments represents four 2-input AND gates. In the case of the scalar notation,
each signal is assigned a unique name: for example, a3, a2, al, and a0. By
comparison, when using vector notation, a single name is applied to a group
of signals, and individual signals within the group are referenced by means of
an index: for example, a[3], a[2], a[l], and a[0]. This means that if we were to
see a schematic (circuit) diagram containing two signals called a3 and a[3], we
would understand this to represent two completely different signals (the former
being a scalar named “a3” and the latter being the third element of a vector
named “a”).
A key advantage of vector notation is that it allows all of the signals
comprising the vector to be easily referenced in a single statement: for example,
a[3:0], b[3:0], and y[3:0]. Thus, vector notation can be used to reduce the size
and complexity of a circuit diagram while at the same time increasing its
clarity.
Equality Corn parators
In some designs it may be necessary to compare two sets of binary values to
see if they contain the same data. Consider a function used to compare two 4-bit
vectors: a[3:0] and b[3:0]. A scalar output called equal is to be set to logic 1 if
each bit in a[3:0] is equal to its corresponding bit in b[3:0]: that is, the vectors
are equal if a[3] = b[3], a[2] = b[2], a[l] = b[l], and a[0] = b[O] (Figure 11-2).
The values on a[3] and b[3] are compared using a 2-input XNOR gate. As
we know from Chapters 5 and 6, if the values on its inputs are the same (both
0s or both Is), the output of an XNOR will be 1, but if the values on its inputs
are different, the output will be 0. Similar comparisons are performed between
the other inputs: a[Z] with b[2], a[l] with b[I], and a[O] with b[O]. The final
AND gate is used to gather the results of the individual comparisons. If all the
inputs to the AND gate are 1, the two vectors are the same, and the output of
the AND gate will be 1. Correspondingly, if any of the inputs to the AND gate
are 0, the two vectors are different, and the output of the AND gate will be 0.
Note that a similar result could have been obtained by replacing the
XNORs with XORs and the AND with a NOR, and that either of these
implementations could be easily extended to accommodate input vectors of
greater width.

