Page 207 - Bebop to The Boolean Boogie An Unconventional Guide to Electronics Fundamentals, Components, and Processes

7 88 Chapter Sixteen
a b c

yy x x ww

\/ \/ \/ \/ \/
/\ /\ /\ /\ /\
-
aa bb G G
+

Programmable Link

Programmed Lin
(Removed)

w X Y
Figure 16-1 4. PLA with one tri-state output configured as an input

Registered Outputs
Certain PLDs are equipped with registers on the outputs, and others with
latches. Depending on the particular device, the registers (or latches) may be
provided on all of the outputs or on a subset of the outputs. Registered devices
are particularly useful for implementing finite state machines (FSMs).13 All of
the registers share a common
dff=D-type flip-flop clock signal (this will be an
I --+7=!rw
enable signal in the case of
latches) which therefore
requires only a single input
pin on the device (Figure
I U 16-15).
dff
In this example, the
outputs are shown as being
registered with D-type flip-
clock
(positive edge)

13 FSMs were introduced in
Figure 16-1 5. PLD with registered outputs Chapter 12.