Page 212 - Bebop to The Boolean Boogie An Unconventional Guide to Electronics Fundamentals, Components, and Processes

Programmable ICs rn 193

devices is paradoxically related to improvements in process technologies that
allow transistors to be made increasingly smaller. The problem is one of scaling,
because not all of the structures on a silicon chip are shrinking at the same rate.
Most notably, the transistors are shrinking faster than the metal interconnections
and, as the features become smaller, a larger percentage of the surface of the die
is covered by metal. This makes it difficult for the EPROM cells to absorb the
ultraviolet and increases the required exposure time.

EEPROMs

A somewhat related technology is that of electrically -erasable programmable
read-only memory (EEPROM or E2PROM). An E2PROM cell is approximately
2.5 times larger than an EPROM cell because it contains two transistors. One
of the transistors is similar to that of an EPROM transistor in that it contains
a floating gate, but the insulating oxide layers surrounding the floating gate
are very much thinner. The second transistor can be used to erase the cell
electrically, and E2PROM devices can typically be erased and reprogrammed
on a word-by-word basis.

FLASH
Finally, a development known as FLASH can trace its ancestry to both
EPROM and E2PROM technologies. The name FLASH was originally coined
to reflect the technology’s rapid erasure times compared to EPROM. Compo-
nents based on FLASH can employ a variety of architectures. Some have a
single floating gate transistor cell with the same area as an EPROM cell, but
with the thinner oxide layers characteristic of an E2PROM component. These
devices can be electrically erased, but only by erasing the whole device or a
large portion of it. Other architectures have a two-transistor cell-which is
very similar to that of an E2PROM cell-allowing them to be erased and
reprogrammed on a word-by-word basis.
Initial versions of FLASH could only store a single bit of data per cell. By
2002, however, technologists were experimenting with a number of different
ways of increasing this capacity. One technique involves storing distinct levels
of charge in the FLASH transistor’s floating gate to represent two bits per cell.
An alternative approach involves creating two distinct storage nodes in a layer
below the gate, thereby supporting two bits per cell.