Page 80 - Building A Succesful Board-Test Strategy

66 BUILDING A SUCCESSFUL BOARD-TEST STRATEGY

project schedules. Revising a fixture to accommodate the frequent changes in board
design or layout that often occur late in a development cycle may also prove very
difficult. Nevertheless, if the board contains 3000 nodes, a dedicated-pin solution
may be prohibitively expensive or unavailable.
In-circuit testers offer numerous advantages. Prices between about $100,000
and $300,000 are generally lower than for high-end functional and some inspec-
tion alternatives, and they are generally less expensive to program than functional
testers. Test times are fast, and although functional testers feature faster test tunes
for good boards, bad-board test and fault-diagnostic times for in-circuit testers can
be substantially lower. In-circuit testers can often verify that even complex boards
have been built correctly.
At the same time, however, three forces are combining to make test genera-
tion more difficult. First, flip-chips, BGAs, and other surface-mount and hidden
node varieties often severely limit bed-of-nails access. In addition, the explosion of
very complex devices increases the burden on tester and CAE vendors to create
device-test programs. As stated in Chapter 1, these tests are not identical to tests
that verify device-design correctness.
Also, as electronic products become both smaller and more complex, hard-
ware designers increasingly rely on ASICs and other custom solutions. Test pro-
grams for these parts must be created by device designers, board designers, or test
engineers. Because ASIC production runs are orders of magnitude lower than pro-
duction runs for mass-marketed devices such as microprocessors and memory
modules, much less time and money are available for test-program creation. Com-
plicating the problem, device designers often do not have final ASIC versions until
very near the release date for the target board or system. Therefore, pressure to
complete test programs in time to support preproduction and early production
stages means that programs are often incomplete.
Perhaps the biggest drawback to in-circuit test is that it provides no assessment
of board performance. Other disadvantages include speed limitations inherent in bed-
of-nails technology, Nails add capacitance to boards under test. In-circuit test speeds
even approaching speeds of today's lightning-fast technologies may seriously distort
stimulus and response signals, as square waves take on distinctly rounded edges.
Traditionally, long distances between tester drivers and receivers often cause
problems as well, especially for digital testing. Impedance mismatches between
signals in the measurement path can cause racing problems, reflections, ringing,
and inappropriate triggering of sequential devices. Fortunately, newer testers pay
much more attention to the architecture's drawbacks by drastically limiting wire
lengths, often to as little as 1 inch.
Board designers dislike the technique because it generally requires a test point
on every board node to allow device access. Overdriving some digital device tech-
nologies can demand currents approaching 1 amp! Obtaining such levels from an
in-circuit tester is difficult at best. In addition, designers express concern that over-
driving components will damage them or at least shorten their useful lives. There-
fore, many manufacturers are opting to forego full in-circuit test, preferring to use