Page 90 - Building A Succesful Board-Test Strategy

76 BUILDING A SUCCESSFUL BOARD-TEST STRATEGY

ing directly to thin mounting plates. Because small pins are more fragile and can
be less accurate, a test fixture should include 100-mil pins wherever possible, resort-
ing to 50-mil and smaller ones only where necessary.

2.3.7 Opens Testing
As stated earlier, the proliferation of surface-mount technologies has aggra-
vated the problem of opens detection to the point where it is now often the most
difficult manufacturing fault to detect. Some such problems, which defy electrical
testing altogether and encourage some kind of inspection, will be addressed in the
next chapter.
Techniques have emerged to detect many opens—assuming (and this assump-
tion is becoming ever more of a constraint) that you have bed-of-nails access to
the board nodes. They perform measurements on unpowered boards, and often
rely on clamp diodes that reside inside the 1C between I/O pins and ground or on
"parasitic diodes" formed by the junction between the pin and the substrate silicon.
The common techniques can be broadly divided into two groups. Parametric
process testing measures voltage or current on the diodes directly or by forming
them into transistors. This approach requires no special hardware beyond the
fixture itself.
The simplest version applies voltage to the diode through the bed-of-nails,
then measures the current. An open circuit generates no current and no forward
voltage. Unfortunately, this method will miss faults on parallel paths.
One variation biases the diode input (emitter) and output (collector) relative
to ground, then compares collector current on groups of pins. Proponents contend
that this approach proves less sensitive to device-vendor differences than the more
conventional alternative. It can detect opens right to the failing pin, as well as mis-
oriented devices and incorrect device types. It will sometimes identify a device from
the wrong logic family, and may find resistive joints and static damage, depending
on their severity.
On the downside, program debugging for this method requires "walking
around" a reference board and opening solder joints. It also may not see differ-
ences between simple devices with the same pinouts but different functions. It
cannot detect faults on power or ground buses, but that limitation is also true with
the other techniques.
In capacitive testing, a spring-mounted metal plate on top of the 1C package
forms one side of a capacitor. The 1C leadframe forms the other side, with the
package material the dielectric. The tester applies an AC signal sequentially to the
device pins through the bed of nails. The probe-assembly buffer senses the current
or the voltage to determine the capacitance. In this case, the measurement circuits
see only the pins, not the bondwire and internal diodes, detecting only opens
between the 1C pins and the board surface. It can, therefore, examine the connec-
tivity of mechanical devices such as connectors and sockets, as well as ICs. Because
of the extra hardware required, this technique increases bed-of-nails fixture costs.