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3.7 / KEY TERMS, REVIEW QUESTIONS, AND PROBLEMS 107

unique transfer request (TR) line.The SBI has 16 such lines (TR0,TR1, . . .,TR15),
with TR0 having the highest priority. When a device wants to use the bus, it places
a reservation for a future time slot by asserting its TR line during the current time
slot. At the end of the current time slot, each device with a pending reservation
examines the TR lines; the highest-priority device with a reservation uses the next
time slot.
A maximum of 17 devices can be attached to the bus. The device with priority
16 has no TR line.Why not?
3.10 On the VAX SBI, the lowest-priority device usually has the lowest average wait time.
For this reason, the processor is usually given the lowest priority on the SBI. Why
does the priority 16 device usually have the lowest average wait time? Under what
circumstances would this not be true?
3.11 For a synchronous read operation (Figure 3.19), the memory module must place the
data on the bus sufficiently ahead of the falling edge of the Read signal to allow for
signal settling.Assume a microprocessor bus is clocked at 10 MHz and that the Read
signal begins to fall in the middle of the second half of T 3 .
a. Determine the length of the memory read instruction cycle.
b. When, at the latest, should memory data be placed on the bus? Allow 20 ns for the
settling of data lines.
3.12 Consider a microprocessor that has a memory read timing as shown in Figure 3.19.
After some analysis, a designer determines that the memory falls short of providing
read data on time by about 180 ns.
a. How many wait states (clock cycles) need to be inserted for proper system opera-
tion if the bus clocking rate is 8 MHz?
b. To enforce the wait states, a Ready status line is employed. Once the processor has
issued a Read command, it must wait until the Ready line is asserted before at-
tempting to read data. At what time interval must we keep the Ready line low in
order to force the processor to insert the required number of wait states?
3.13 A microprocessor has a memory write timing as shown in Figure 3.19. Its manufac-
turer specifies that the width of the Write signal can be determined by T 50, where
T is the clock period in ns.
a. What width should we expect for the Write signal if bus clocking rate is 5 MHz?
b. The data sheet for the microprocessor specifies that the data remain valid for
20 ns after the falling edge of the Write signal. What is the total duration of valid
data presentation to memory?
c. How many wait states should we insert if memory requires valid data presentation
for at least 190 ns?
3.14 A microprocessor has an increment memory direct instruction, which adds 1 to the
value in a memory location. The instruction has five stages: fetch opcode (four bus
clock cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1
to operand (three cycles), and store operand (three cycles).
a. By what amount (in percent) will the duration of the instruction increase if we
have to insert two bus wait states in each memory read and memory write
operation?
b. Repeat assuming that the increment operation takes 13 cycles instead of 3 cycles.
3.15 The Intel 8088 microprocessor has a read bus timing similar to that of Figure 3.19, but
requires four processor clock cycles. The valid data is on the bus for an amount of
time that extends into the fourth processor clock cycle.Assume a processor clock rate
of 8 MHz.
a. What is the maximum data transfer rate?
b. Repeat but assume the need to insert one wait state per byte transferred.
3.16 The Intel 8086 is a 16-bit processor similar in many ways to the 8-bit 8088. The 8086
uses a 16-bit bus that can transfer 2 bytes at a time, provided that the lower-order
byte has an even address. However, the 8086 allows both even- and odd-aligned