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108 CHAPTER 3 / A TOP-LEVEL VIEW OF COMPUTER FUNCTION

word operands. If an odd-aligned word is referenced, two memory cycles, each con-
sisting of four bus cycles, are required to transfer the word. Consider an instruction
on the 8086 that involves two 16-bit operands. How long does it take to fetch the
operands? Give the range of possible answers.Assume a clocking rate of 4 MHz and
no wait states.
3.17 Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16-
bit microprocessor. Assume that, on average, 20% of the operands and instructions
are 32 bits long, 40% are 16 bits long, and 40% are only 8 bits long. Calculate the im-
provement achieved when fetching instructions and operands with the 32-bit micro-
processor.
3.18 The microprocessor of Problem 3.14 initiates the fetch operand stage of the incre-
ment memory direct instruction at the same time that a keyboard actives an interrupt
request line. After how long does the processor enter the interrupt processing cycle?
Assume a bus clocking rate of 10 MHz.
3.19 Draw and explain a timing diagram for a PCI write operation (similar to Fig-
ure 3.23).

APPENDIX 3A TIMING DIAGRAMS

In this chapter, timing diagrams are used to illustrate sequences of events and de-
pendencies among events. For the reader unfamiliar with timing diagrams, this ap-
pendix provides a brief explanation.
Communication among devices connected to a bus takes place along a set of
lines capable of carrying signals.Two different signal levels (voltage levels), repre-
senting binary 0 and binary 1, may be transmitted. A timing diagram shows the
signal level on a line as a function of time (Figure 3.27a). By convention, the
binary 1 signal level is depicted as a higher level than that of binary 0. Usually, bi-
nary 0 is the default value. That is, if no data or other signal is being transmitted,
then the level on a line is that which represents binary 0. A signal transition from
0 to 1 is frequently referred to as the signal’s leading edge; a transition from 1 to 0
is referred to as a trailing edge. Such transitions are not instantaneous, but this
transition time is usually small compared with the duration of a signal level. For
clarity, the transition is usually depicted as an angled line that exaggerates the rel-
ative amount of time that the transition takes. Occasionally, you will see diagrams
that use vertical lines, which incorrectly suggests that the transition is instanta-
neous. On a timing diagram, it may happen that a variable or at least irrelevant
amount of time elapses between events of interest.This is depicted by a gap in the
time line.
Signals are sometimes represented in groups (Figure 3.27b). For example, if
data are transferred a byte at a time, then eight lines are required. Generally, it is not
important to know the exact value being transferred on such a group, but rather
whether signals are present or not.
A signal transition on one line may trigger an attached device to make signal
changes on other lines. For example, if a memory module detects a read control
signal (0 or 1 transition), it will place data signals on the data lines. Such cause-and-
effect relationships produce sequences of events. Arrows are used on timing dia-
grams to show these dependencies (Figure 3.27c).