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104 CHAPTER 3 / A TOP-LEVEL VIEW OF COMPUTER FUNCTION

e. The bus arbiter samples all REQ lines at the beginning of clock 3 and makes
an arbitration decision to grant the bus to B for the next transaction. It then
asserts GNT-B and deasserts GNT-A. B will not be able to use the bus until it
returns to an idle state.
f. A deasserts FRAME to indicate that the last (and only) data transfer is in
progress. It puts the data on the data bus and signals the target with IRDY.The
target reads the data at the beginning of the next clock cycle.
g. At the beginning of clock 5, B finds IRDY and FRAME deasserted and so is
able to take control of the bus by asserting FRAME. It also deasserts its REQ
line, because it only wants to perform one transaction.

Subsequently, master A is granted access to the bus for its next transaction.
Notice that arbitration can take place at the same time that the current bus
master is performing a data transfer.Therefore, no bus cycles are lost in performing
arbitration.This is referred to as hidden arbitration.

3.6 RECOMMENDED READING AND WEB SITES

The clearest book-length description of PCI is [SHAN99]. [ABBO04] also contains a lot of
solid information on PCI.

ABBO04 Abbot, D. PCI Bus Demystified. New York: Elsevier, 2004.
SHAN99 Shanley, T., and Anderson, D. PCI Systems Architecture. Richardson, TX:
Mindshare Press, 1999.

Recommended Web sites:

• PCI Special Interest Group: Information about PCI specifications and products
• PCI Pointers: Links to PCI vendors and other sources of information

3.7 KEY TERMS, REVIEW QUESTIONS,AND PROBLEMS

Key Terms

address bus distributed arbitration memory address register
asynchronous timing instruction cycle (MAR)
bus instruction execute memory buffer register (MBR)
bus arbitration instruction fetch peripheral component
bus width interrupt interconnect (PCI)
centralized arbitration interrupt handler synchronous timing
data bus interrupt service routine system bus
disabled interrupt