Page 129 -

9

i

8 Data transfer

DATA-3 Byte enable
h Data phase Wait state

7 Wait

g

DATA-2
6 Data transfer
Byte enable Data phase Wait state

5 Wait Bus transaction

DATA-1 e f

4 Data transfer
Byte enable Data phase Wait state

d

3 Wait

c
ADDRESS BUS CMD
b
2 Address phase

a PCI Read Operation

1

CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# Figure 3.23

101