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3.5 / PCI 99

PCI Commands
Bus activity occurs in the form of transactions between an initiator, or master, and a
target. When a bus master acquires control of the bus, it determines the type of
transaction that will occur next. During the address phase of the transaction, the
C/BE lines are used to signal the transaction type.The commands are as follows:
• Interrupt Acknowledge
• Special Cycle
• I/O Read
• I/O Write
• Memory Read
• Memory Read Line
• Memory Read Multiple
• Memory Write
• Memory Write and Invalidate
• Configuration Read
• Configuration Write
• Dual address Cycle
Interrupt Acknowledge is a read command intended for the device that func-
tions as an interrupt controller on the PCI bus.The address lines are not used during
the address phase, and the byte enable lines indicate the size of the interrupt identi-
fier to be returned.
The Special Cycle command is used by the initiator to broadcast a message to
one or more targets.
The I/O Read and Write commands are used to transfer data between the initia-
tor and an I/O controller. Each I/O device has its own address space, and the address
lines are used to indicate a particular device and to specify the data to be transferred
to or from that device.The concept of I/O addresses is explored in Chapter 7.
The memory read and write commands are used to specify the transfer of a
burst of data, occupying one or more clock cycles. The interpretation of these com-
mands depends on whether or not the memory controller on the PCI bus supports
the PCI protocol for transfers between memory and cache. If so, the transfer of data
3
to and from the memory is typically in terms of cache lines, or blocks. The three
memory read commands have the uses outlined in Table 3.5. The Memory Write
command is used to transfer data in one or more data cycles to memory. The Mem-
ory Write and Invalidate command transfers data in one or more cycles to memory.
In addition, it guarantees that at least one cache line is written. This command sup-
ports the cache function of writing back a line to memory.
The two configuration commands enable a master to read and update configu-
ration parameters in a device connected to the PCI. Each PCI device may include

3 The fundamental principles of cache memory are described in Chapter 4; bus-based cache protocols are
described in Chapter 17.