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96 CHAPTER 3 / A TOP-LEVEL VIEW OF COMPUTER FUNCTION

Processor

Cache
Motion
Bridge/ Audio video
memory DRAM
controller

PCI Bus

LAN SCSI Expansion
bus bridge Graphics
Base I/O
devices

Expansion bus

(a) Typical desktop system

Processor/ Processor/ Memory
cache cache controller DRAM

System bus

Host bridge Host bridge

PCI Bus PCI Bus

Expansion Expansion SCSI SCSI LAN LAN
bus bridge bus bridge
PCI to PCI
bridge

(b) Typical server system
Figure 3.22 Example PCI Configurations

• Arbitration pins: Unlike the other PCI signal lines, these are not shared lines.
Rather, each PCI master has its own pair of arbitration lines that connect it di-
rectly to the PCI bus arbiter.
• Error reporting pins: Used to report parity and other errors.