Page 12 - DSP Integrated Circuits

Contents xi

11.5 Bit-Parallel Arithmetic 472
11.5.1 Addition and Subtraction 472
11.5.2 Bit-Parallel Multiplication 475
11.5.3 Shift-and-Add Multiplication 476
11.5.4 Booth's Algorithm 477
11.5.5 Tree-Based Multipliers 478
11.5.6 Array Multipliers 479
11.5.7 Look-Up Table Techniques 481
11.6 Bit-Serial Arithmetic 481
11.6.1 Bit-Serial Addition and Subtraction 482
11.6.2 Bit-Serial Multiplication 482
11.6.3 Serial/Parallel Multiplier 482
11.6.4 Transposed Serial/Parallel Multiplier 485
11.6.5 S/P Multiplier-Accumulator 486
11.7 Bit-Serial Two-Port Adaptor 486
11.8 S/P Multipliers with Fixed Coefficients 489
11.8.1 S/P Multipliers with CSDC Coefficients 490
11.9 Minimum Number of Basic Operations 491
11.9.1 Multiplication with a Fixed Coefficient 492
11.9.2 Multiple-Constant Multiplications 495
11.10 Bit-Serial Squarers 496
11.10.1 Simple Squarer 496
11.10.2 Improved Squarer 498
11.11 Serial/Serial Multipliers 500
11.12 Digit-Serial Arithmetic 502
11.13 The CORDIC Algorithm 502
11.14 Distributed Arithmetic 503
11.14.1 Distributed Arithmetic 503
11.14.2 Parallel Implementation of Distributed Arithmetic 507
11.15 The Basic Shift-Accumulator 507
11.16 Reducing the Memory Size 510
11.16.1 Memory Partitioning 510
11.16.2 Memory Coding 511
11.17 Complex Multipliers 512
11.18 Improved Shift-Accumulator 514
11.18.1 Complex Multiplier Using Two-Phase Logic 515
11.18.2 Complex Multiplier Using TSPC Logic 515
11.19 FFT Processor, Cont. 516
11.19.1 Twiddle Factor PE 517
11.19.2 Control PEs 520
11.19.3 Address PEs 520
11.19.4 Base Index Generator 521
11.19.5 RAM Address PEs 522
11.20 DCT Processor, Cont. 522