Page 8 - DSP Integrated Circuits

Contents vii

5.10 Interpolator, Cont. 218
5.11 FFT Processor, Cont. 218
5.12 DCT Processor, Cont. 218

6 DSP Algorithms 225

6.1 Introduction 225
6.2 DSP Systems 225
6.2.1 DSP Algorithms 226
6.2.2 Arithmetic Operations 228
6.3 Precedence Graphs 229
6.3.1 Parallelism in Algorithms 229
6.3.2 Latency 230
6.3.3 Sequentially Computable Algorithms 233
6.3.4 Fully Specified Signal-Flow Graphs 234
6.4 SFGs in Precedence Form 234
6.5 Difference Equations 239
6.6 Computation Graphs 243
6.6.1 Critical Path 243
6.6.2 Equalizing Delay 243
6.6.3 Shimming Delay 244
6.6.4 Maximum Sample Rate 245
6.7 Equivalence Transformations 247
6.7.1 Essentially Equivalent Networks 248
6.7.2 Timing of Signal-Flow Graphs 249
6.7.3 Minimizing the Amount of Shimming Delay 251
6.7.4 Maximally Fast Critical Loops 251
6.8 Interleaving and Pipelining 253
6.8.1 Interleaving 254
6.8.2 Pipelining 255
6.8.3 Functional and Structural Pipelines 259
6.8.4 Pipeline Interleaving 260
6.9 Algorithm Transformations 261
6.9.1 Block Processing 261
6.9.2 Clustered Look-Ahead Pipelining 263
6.9.3 Scattered Look-Ahead Pipelining 266
6.9.4 Synthesis of Fast Filter Structures 267
6.10 Interpolator, Cont. 267

7 DSP System Design 277

7.1 Introduction 277
7.2 A Direct Mapping Technique 278