Page 10 - DSP Integrated Circuits

Contents ix

8.3.3 TMS320C25™andTMS320C50™ 361
8.3.4 TMS320C30™ 362
8.3.5 TMS320C40™ 363
8.3.6 Motorola DSP56001™ and DSP56002™ 363
8.3.7 Motorola DSP96001™ and DSP96002™ 364
8.4 Ideal DSP Architectures 365
8.4.1 Processing Elements 366
8.4.2 Storage Elements 367
8.4.3 Interconnection Networks 367
8.4.4 Control 367
8.4.5 Synchronous and Asynchronous Systems 368
8.4.6 Self-Timed Systems 368
8.4.7 Autonomous Bit-Serial PEs 369
8.5 Multiprocessors And Multicomputers 370
8.6 Message-Based Architectures 371
8.6.1 Interconnection Topologies 372
8.7 Systolic Arrays 374
8.8 Wave Front Arrays 376
8.8.1 Datawave™ 377
8.9 Shared-Memory Architectures 379
8.9.1 Memory Bandwidth Bottleneck 380
8.9.2 Reducing the Memory Cycle Time 380
8.9.3 Reducing Communications 381
8.9.4 Large Basic Operations 383

9 Synthesis of DSP Architectures 387
9.1 Introduction 387
9.2 Mapping of DSP Algorithms onto Hardware 388
9.2.1 Design Strategy 388
9.3 Uniprocessor Architectures 389

9.4 Isomorphic Mapping of SFGs 394
9.4.1 Cathedral I 395
9.5 Implementations Based on Complex PEs 397
9.5.1 Vector-Multiplier-Based Implementations 397
9.5.2 Numerically Equivalent Implementation 399
9.5.3 Numerically Equivalent Implementations of WDFs 402
9.6 Shared-Memory Architectures with Bit-Serial PEs 404
9.6.1 Minimizing the Cost 405
9.6.2 Uniform Memory Access Rate 405
9.6.3 Fast Bit-Serial Memories 407
9.6.4 Balancing the Architecture 407
9.6.5 Mode of Operation 408
9.6.6 Control 409