Page 13 - DSP Integrated Circuits

xii Contents

12 Integrated Circuit Design 531
12.1 Introduction 531
12.2 Layout of VLSI Circuits 531
12.2.1 Floor Planning and Placement 532
12.2.2 Floor Plans 533
12.2.3 Global Routing 534
12.2.4 Detailed Routing 534
12.2.5 Compaction by Zone Refining 536
12.3 Layout Styles 537
12.3.1 The Standard-Cell Design Approach 537
12.3.2 The Gate Array Design Approach 539
12.3.3 The Sea-of-Gates Design Approach 541
12.3.4 The Unconstrained-Cell Design Approach 541
12.3.5 The Unconstrained Design Approach 544
12.4 FFT Processor, Cont. 545
12.5 DCT Processor, Cont. 547
12.6 Interpolator, Cont. 548
12.7 Economic Aspects 551
12.7.1 Yield 551

Index 555