Page 9 - DSP Integrated Circuits

viii Contents

7.3 FFT Processor, Cont. 280
7.3.1 First Design Iteration 281
7.3.2 Second Design Iteration 283
7.3.3 Third Design Iteration 290
7.4 Scheduling 292
7.5 Scheduling Formulations 293
7.5.1 Single Interval Scheduling Formulation 294
7.5.2 Block Scheduling Formulation 297
7.5.3 Loop-Folding 297
7.5.4 Cyclic Scheduling Formulation 298
7.5.5 Overflow and Quantization 305
7.5.6 Scheduling of Lattice Wave Digital Filters 310
7.6 Scheduling Algorithms 313
7.6.1 ASAP and ALAP Scheduling 313
7.6.2 Earliest Deadline and Slack Time Scheduling 314
7.6.3 Linear Programming 315
7.6.4 Critical Path List Scheduling 315
7.6.5 Force-Directed Scheduling 315
7.6.6 Cyclo-Static Scheduling 317
7.6.7 Maximum Spanning Tree Method 320
7.6.8 Simulated Annealing 321
7.7 FFT Processor, Cont. 323
7.7.1 Scheduling of the Inner Loops 325
7.7.2 Input and Output Processes 327
7.8 Resource Allocation 328
7.8.1 Clique Partitioning 330
7.9 Resource Assignment 331
7.9.1 The Left-Edge Algorithm 331
7.10 Interpolator, Cont. 334
7.10.1 Processor Assignment 336
7.10.2 Memory Assignment 336
7.10.3 Memory Cell Assignment 338
7.11 FFT Processor, Cont. 341
7.11.1 Memory Assignment 341
7.11.2 Butterfly Processor Assignment 344
7.11.3 Input and Output Process Assignment 347
7.12 DCT Processor, Cont. 348

8 DSP Architectures 357
8.1 Introduction 357
8.2 DSP System Architectures 357
8.3 Standard DSP Architectures 359
8.3.1 Harvard Architecture 360
8.3.2 TMS32010™ 360