Page 142 - DSP Integrated Circuits

4.5 IIR Filters 127

Company Model Description
Inmos A100 4-, 8-, 12-, or 16-bit coeff., 16-bit input data, 16 x 16-bit
mult, with 36-bit accum., and 24-bit-rounded output
32-taps (fixed length)
Throughput
15.00 MHz, 4-bit coeff., 3.75 MHz, 16-bit coeff
84-pin PGA-flatpack package
Harris HSP43891 9-bit coeff., 9-bit input data, 9 x 9-bit mult, with 26-bit
accum., and 26-bit output
8 taps per device
Throughput 30 MHz
Support for decimation by 2, 3, or 4
High-speed synchronous inputs and outputs
84-pin PGA-PLCC package
Harris HSP43881 8-bit coeff., 8-bit input data, 8 x 8-bit mult, with 26-bit
accum., and 26-bit output
8 taps per device
Throughput 30 MHz
Support for decimation by 2, 3, or 4
84-pin PGA-PLCC package
Harris HSP43168 10-bit data and coeff
Dual FIR with 8 taps or single FIR with 16 taps
Support for decimation up to a factor 16
Throughput 40 MHz
84-pin PGA-PLCC package
Harris HSP43220 20-bit coeff. and 16-bit input data
Two-stage FIR filter for decimation. The first stage can
decimate with a factor up to 1024. The second stage has
up to 512 taps and can decimate with a factor 16.
Throughput 30 MHz
84-pin PGA-PLCC package
Motorola DSP56200 24-bit coeff., 16-bit input data, 24 x 16-bit mult, with 40-
bit accum. 32-bit or 16-bit-rounded output.
4-256 taps (selectable)
Throughput
Single FIR filter
227 kHz, 32-taps, 1-device, 37 kHz, 256-taps, 1-device, 37
kHz, 1024-taps, 4-devices
Two FIR filters: 123 kHz, 32-taps, 1-device, 36 kHz, 128-
taps, 1-device
Adaptive FIR filter: 19 kHz, 256-taps, 1-device, 19 kHz,
1024-taps, 4-devices, 115 kHz, 256-taps, 8-devices
28-pin DIP package
Table 4.1 FIR filter chips

4.5 IIR FILTERS

Digital FIR filters can only realize transfer functions with effective poles at the
origin of the z-plane, while IIR niters can have poles anywhere within the unit cir-
cle. Hence, in IIR niters the poles can be used to improve the frequency selectivity.
As a consequence, the required filter order is much lower for IIR as compared to