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4                                            Chapter 1 DSP Integrated Circuits


            Early standard digital signal processors were based on the Harvard architec-
        ture that has two buses and separate memories for data and instructions. Gener-
        ally, standard digital signal processors are provided with MACs—multiplier-
        accumulators—in order to perform sum-of-product computations efficiently. The
        high performance of these processors is achieved by using a high degree of paral-
        lelism. Typically, a multiply-and-add, data fetch, instruction fetch and decode, and
        memory pointer increment or decrement can be done simultaneously. Typical
        drawbacks are the limited on-chip memory size and the relatively low I/O band-
        width. The architectures used in modern standard digital signal processors will be
        further discussed in Chapter 8.
            Early signal processors used fixed-point arithmetic and often had too short
        internal data word length (16 bits) and too small on-chip memory to be really effi-
        cient. Recent processors use floating-point arithmetic which is much more expensive
        than fixed-point arithmetic in terms of power consumption, execution time, and chip
        area. In fact, these processors are not exclusively aimed at DSP applications. Appli-
        cations that typically require floating-point arithmetic are SD-graphics, multimedia,
        and mechanical CAD applications. Fixed-point arithmetic is better suited for DSP
        applications than floating-point arithmetic since good DSP algorithms require high
        accuracy (long mantissa), but not the large dynamic signal range provided by float-
        ing-point arithmetic. Further, problems due to nonlinearities (rounding of products)
        are less severe in fixed-point arithmetic. Hence, we conclude that the current gener-
        ation of standard signal processors is not efficient for many DSP applications.



        1.4 APPLICATION-SPECIFIC ICs FOR DSP

        The development effort for a large integrated circuit typically ranges between 1
        and 10 man-years, depending on the uniqueness of the function, performance con-
        straints, and the availability and performance of design tools. The combined
        advances in system design capability and VLSI technology have made it possible
        to economically design unique integrated circuits for use in dedicated applications,
        so-called application-specific integrated circuits (ASICs) [14]. This option makes
        new innovative system solutions practical.
            The possibility of incorporating a whole signal processing system into one chip
        has a multitude of effects. It will dramatically increase the processing capacity and
        simultaneously reduce the size of the system, the power consumption, and the pin-
        restriction problem, which may be severe when a system has to be implemented
        using several chips. Reliability will also increase when the number of pins and the
        working temperature of the chips are reduced. Although VLSI technology solves or
        circumvents many problems inherent in older technologies, new limits and draw-
        backs surface. The main problems originate from the facts that the systems to be
        designed tend to be very complex and are often implemented in the most advanced
        VLSI process available. The latter has the adverse effect that the system often must
        be designed by using untested building blocks and incomplete and unproved CAD
        tools. Because of the innovative and dynamic nature of DSP techniques, the design
        team often lacks experience, since a similar system may not have been designed
        before. These factors make it difficult to estimate accurately the time it will take for
        the whole design process up to the manufacture of working chips.
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