Page 289 - DSP Integrated Circuits

274 Chapter 6 DSP Algorithms

Figure P6.16

6.17 Determine the maximum sample rate for
(a) The LMS algorithm,
(b) The RLS algorithm that was discussed in Chapter 3.
6.18 How is the frequency response of a digital filter affected by pipelining?
6.19 Discuss the meaning of pipelining at the algorithmic and digital circuit
levels. Discuss especially pipelining of bit-serial arithmetic.
6.20 Show how the filter in Example 4.16 can be pipelined. Assume that addition
and multiplication are atomic operations. Also, find the system of difference
equation in computable order for the pipelined filter.
6.21 How many useful pipeline levels can be introduced in the filters in Examples
4.11, 4.12, and 4.16, respectively? Assume that the two-port adaptors are
atomic operations.

6.22 Determine the shimming delays required in a third-order FIR filter realized in
(a) Direct form,
(b) Transposed direct form.

The filter is implemented using bit-serial arithmetic. The data word length is
16 bits and the coefficient word length is 12 bits. Multiplication takes 12 and
addition 1 clock cycle.
6.23 Show that for block processing of an Nth order filter
(a) The number of operations per sample is given by Equation (6.5).
(b) The minimum operation rate is N s ~ 2(2 + J2 )N which is obtained for
L = JN(2N-1) « 72 N.
2
(c) The number of multipliers required to achieve T mi n is (N + L) .
6.24 Determine the transfer function and the corresponding difference equation
for a pipelined first-order all-pole section using:
(a) Clustered look-ahead pipelining.
(b) Scattered look-ahead pipelining.