Page 390 - DSP Integrated Circuits
P. 390
8.7 Systolic Arrays 375
Usually, the PEs are identical and perform identical operations, but in some
cases several types of PEs or operations are required. Unlike other parallel archi-
tectures employing a lattice of PEs, a systolic array is characterized by a regular
data flow. Typically, two or more data streams flow through the cells of the systolic
arrays with various speeds and directions. Data items from different streams
interact with each other and trigger computations in the PEs where they meet. A
systolic array is an ^-dimensional structural pipeline with synchronous communi-
cation between the PEs. Thus, a systolic array simultaneously exploits both pipe-
lining and parallelism in the algorithm.
We illustrate the basic principle of systolic arrays by a simple example.
EXAMPLE 8.1
Figure 8.22 illustrates the basic principle of systolic arrays.
The array implements a matrix multiplication
where the sizes of A and B are 4x4. The A and B matrices are applied from the
left side and from the top of the array. The PEs accept data from the left and top
Figure 8.22 Systolic array for matrix multiplication