Page 400 - DSP Integrated Circuits
P. 400
Problems 385
PROBLEMS
8.1 Define in what sense an architecture can be ideal. State suitable criteria for
an ideal DSP architecture
8.2 What are the main limitations in shared memory architectures? Discuss
different approaches in overcoming or reducing these limitations?
8.3 Determine the peak performance and I/O data rate for the Datawave™ chip
if I/O takes two clock cycles.
8.4 Compare the various standard fixed-point DSPs with respect to power
consumption per sample for some typical algorithms—for example, FIR
filters and second-order sections.
8.5 Determine maximum throughput for the autonomous PE shown in Figure
8.12. Assume that the PE is a multiplier with a coefficient word length of W c
and that the data word length is Wj > W c.
8.6 Estimate the required chip area and achievable clock frequency if the
processor TMS320C25 would be implemented using a 0.35-um CMOS process.
Assume for sake of simplicity that the original and new CMOS processes have
the same number of metal layers.
