Page 405 - DSP Integrated Circuits

390 Chapter 9 Synthesis of DSP Architectures

data and coefficient word lengths are too short. Typical word lengths are in the
range of 18 to 24 bits.
Generally, the power consumption of standard signal processors is large. Note
that floating-point arithmetic may also provide too low an accuracy—i.e., the man-
tissa is too short. In fact, digital signal processing generally requires high accu-
racy, but the dynamic range requirement is comparatively low.
Application-specific architectures using only one processor are of great impor-
tance when the application has a relatively low work load and stringent require-
ments on low power dissipation—for example, in battery powered applications. A
number of such architectures are discussed in this section.

EXAMPLE 9.1
Figure 9.4 shows a block diagram for a single PE (multiplier-accumulator) archi-
tecture for FIR filters in direct form [4] that implements the convolution:

Figure 9.4 Single PE architecture for the direct form FIR filter structure

Data are processed bit-serially and stored in a long shift register. The multi-
plier accepts data in bit-serial form and coefficients in bit-parallel form. The
design of such serial/parallel multipliers will be discussed in Chapter 11. The filter
coefficients are therefore stored bit-parallel in a ROM. Determine how the output
values are computed.
The operation of the FIR filter is illustrated in Table 9.1. The computations start
x n
with a cleared accumulator register. In the first time step the product ajv-1 ( -N +T)
is computed and added to the cleared accumulator, and x(n) is loaded into the first
shift register position. In the next time step the shift register is shifted, and the
x n
product dN_2 ( —N+2)is computed and added to the accumulator.