Page 402 - DSP Integrated Circuits

SYNTHESIS OF DSP

ARCHITECTURES

9.1 INTRODUCTION

Digital signal processing has, as a result of the development of robust and efficient
algorithms and advances in VLSI technology, attained widespread use. A major
factor in this development is the independence of element sensitivity inherent in
digital systems. The advent of commercially available digital signal processors fur-
ther increased the competitiveness of digital over analog signal processing tech-
niques. However, DSP-based implementations are generally not competitive for
low- to medium-performance and low-cost systems. SC techniques are often more
suitable for these types of applications. Other difficult DSP applications are sys-
tems with very high sampling rates and large computational work loads.
We believe that the somewhat limited success in designing competitive, cost-
effective DSP systems is largely due to the lack of general and systematic proce-
dures for exploring the computational properties of the algorithm and synthesis
procedures for the corresponding optimal circuit architectures. We will therefore
focus on design techniques that match the architecture to the algorithm and not
vice versa.
In previous chapters we have discussed the problems of scheduling opera-
tions and subsequent resource allocation and assignment. As a result of these
design steps a class of ideal architectures was defined. The type and number of
PEs, and the size and number of memories, including the required communica-
tion channels, were determined. The required control signals, component perfor-
mance requirements (e.g., TPE, TM, and communication channel bandwidths)
were also derived in these design steps. In this chapter we will present methods
of synthesizing optimal architectures based upon these results. The synthesis
process leads to a wide class of shared-memory architectures that can be designed
to have a good balance between communication bandwidth and processing capac-
ity. We will also discuss a few simple cases where the scheduling, resource alloca-
tion, and assignment steps are trivial. In the first case all of the processes are
mapped onto a single processor. This approach leads to power- and area-efficient

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