Page 404 - DSP Integrated Circuits

9.3 Uniprocessor Architectures 389

number of processing elements, memories, communication channels, and the con-
trol for a class of ideal architectures.
In the next design step, the best candidate
among these architectures is chosen and optimized
subject to the system requirements. However, sched-
uling assumes an underlying hardware architec-
ture—for example, types of processing elements and
number of memories. Therefore we assume that the
scheduling of the processes is fixed when we explore
the architectural candidates for a given schedule.
Another schedule leads to another set of architec-
tural alternatives. Hence, the synthesis process is
essentially downward, as illustrated in Figure 9.2,
but the design steps are highly interdependent. If the
requirements can not be met in a certain design step,
the synthesis process has to be restarted at an earlier
stage. Possibly a better algorithm has to be chosen. In
some cases it may be necessary to continue upward in
the hierarchy and redesign the basic building blocks,
choose a better process technology, etc.
The choice of a particular algorithm determines
the class of usable architectures. Therefore, the syn-
thesis process must in practice be followed by an
evaluation phase and possibly by a subsequent rede-
sign iteration involving the selection of another algo-
rithm. The design process may have to be iterated
several times in order to arrive at a satisfactory solu-
tion. It may also have to be extended to a lower level
Figure 9.2 Synthesis path
of abstraction—for example, to the logic and electri- for optimal
cal circuit levels. architectures

9.3 UNIPROCESSOR ARCHITECTURES

Conceptually the simplest approach to
implementing a DSP algorithm is to use a
standard digital signal processor. The use of
only one processor represents an extreme
point in the resource-time domain. Figure
9.3 illustrates the major steps in the imple-
mentation process. Any sequential schedule
for the DSP algorithm is acceptable. Pro-
gramming standard digital signal proces-
sors is therefore simple, but the long
execution time is a severe drawback. Advan-
tages with this approach are that decision
making and irregular algorithms can be eas- Figure 9.3 Mapping of the operations
ily accommodated. A common drawback of onto a single processing
standard digital signal processors is that element.