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1.7 Integrated Circuit Design 29

[12] Lawson H.W.: Philosophies for Engineering Computer-Based Systems, IEEE
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[13] Leung S.S., Fisher P.D., and Shanblatt M.A.: A Conceptual Framework for
ASIC Design, Proc. IEEE, Vol. 76, No. 7, pp. 741-755, July 1988.
[14] Preas B. and Lorenzetti M. (eds.): Physical Design Automation of VLSI
Systems, Benjamin/Cummings, Menlo Park, CA, 1988.
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PROBLEMS

1.1 (a) Describe briefly a systematic partitioning technique for the design of a
complex DSP system. Also give a motivation for the chosen partitioning
technique.
(b) Describe the different types of transformations between two adjacent
levels of abstraction in the design process. Also describe different types
of transformations within a design level.
(c) Define the following concepts and provide an example for each concept:
Abstraction Hierarchical abstraction
Modularity Regularity
Architecture Standard
1.2 (a) What are the basic components of a specification? Provide an example.
(b) Give an example and a counterexample of a behavioral description.
(c) Give an example and a counterexample of an abstraction.
1.3 Describe the main features of a structured design methodology.

1.4 Discuss advantages and disadvantages of an ASIC implementation
compared to a software implementation of a DSP system.
1.5 Discuss possibilities to reduce various types of complexity in a system based
on the standard and ASIC processor approaches.
a
1.6 Show that ln(n) e O(n ) where a > O.That is, ln(/i) grows more slowly than
any power of n.
n
k
1.7 Show that n e O(a ) where k > 0. That is, powers ofn grow more slowly than
n
any exponential function, a , where a > 0.
1.8 Compare the execution time for algorithms with the complexity of: OOi),
2 3
O(n log(Ai)), O(n ), and O(n ) for different problem sizes—for example,
n = 10,100,1000,10000, and 100000.
1.9 (a) Discuss how different design views are supported by VHDL.
(b) Discuss how VHDL supports different methods to reduce the design
complexity.
1.10 Derive behavioral, data-flow, and structural descriptions of a full-adder.