Page 42 - DSP Integrated Circuits

1.7 Integrated Circuit Design 27

Drive capacity for internal buffers
Circuit area, yield, and packaging
Temperature and voltage effects
Maximum and minimum temperatures, voltages, etc.
Process technology

DESIGN-EFFORT-RELATED
CAD tools
Layout style
Regularity and modularity of the circuits
Module generators
Cell library

The aim is to determine if the system can be built using the given approach. If
not, another approach has to be tried or the system requirement has to be relaxed.
If a good feasible solution has been found, it can serve as a starting point for the
subsequent design process. The design process involves technical trade-offs
between system performance, costs, and design effort.

1.7.3 System Partitioning

It is usually advantageous to implement the whole system on a single chip, since
external communication is comparatively slow and expensive in terms of power
consumption. Since DSP algorithms are characterized by high-speed communica-
tion between different parts of the algorithm, it is often difficult to partition the
system into several chips that communicate at low speed.
The achievable throughput in a multichip DSP system will ultimately be lim-
ited by the I/O bandwidth as the feature size of integrated circuit technologies are
scaled down. Scaling down devices does not significantly increase bandwidth of off-
chip communication; it mainly increases the internal speed of the circuit. A future
solution may be to use new I/O techniques—optoelectronics, for example. Hence,
the high computational capacity in highly parallel architectures may be difficult to
exploit because of the mundane problem of getting data on and off the chip. There-
fore, system solutions that have high computational complexity per input sample
will undoubtedly benefit from advances expected in integrated circuit technologies.
A practical approach to system partitioning is to begin by estimating system
size in terms of transistor devices needed for memories and logic. The number of
chips required can then be estimated by observing the following constraints:
2
Q Assume that the largest economical chip area is, for example, 100 mm .
Allocate the parts of the system to different chips, taking device density
into account.
Q The system must be partitioned such that the number of I/O-pins fits the
packages, and the power dissipation in each package is not too large. Note
that there are rarely any pin-out problems in systems with bit-serial
communication.
Q The partitioning must lead to reasonable chip-to-chip communication times.
After a good partitioning has been obtained, it can be refined using computer-
based methods. Many such partitioning methods have been proposed. The starting