Page 38 - DSP Integrated Circuits

1.6 DSP System Design 23

entity OR_gate is
port(Ini, In2'. in Bit; Outi: out Bit);
end OR_gate;
-- ARCHITECTURAL BODIES
architecture Behavior_desc of Half_Adder is
begin
process
begin
Sum <= X or Y after 5 ns;
Carry <= X and Y after 5 ns;
wait on X, Y;
end process;
end Behavior_desc;
architecture Behavior_desc of OR_gate is
begin
process
begin
Outi <= Ini or In2 after 5 ns;
wait on Ini, In£;
end process;
end Behavior_desc;

-- ENTITY DECLARATION
entity Full_Adder is
port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);
end Full_Adder;
-- ARCHITECTURAL BODY
architecture Structure of Half_Adder is
— Signal declarations
signal Temp_sum, Temp_carryi, Temp_carry2: Bit;

— Local declarations
component HA
port(X, Y: in Bit; Sum, Carry: out Bit);
end component HA;
component OG
port(Ini, In2: in Bit; Outi: out Bit);
end component OG;
for UQ: HA use entity Half_Adder(Behavior_desc);
for Ui: HA use entity Half_Adder(Behavior_desc);
for U^. OG use entity OR_gate(Behavior_desc);
begin-- Connect the ports of the components
U 0:HA
port(X => A, Y => B, Sum => Temp_sum, Carry => Temp_carryi);
Ui:HA
port(X => Temp_sum, Y => Carry_in, Sum => Sum, Carry => Temp_carry2);
U 2:OG
portdni => Temp_carryi, In2 => Temp_carry2, Outj => Carry_out);
end Structure;

Box 1.2. VHDL description of a half-adder and a full-adder