Page 39 - DSP Integrated Circuits

24 Chapter 1 DSP Integrated Circuits

Note that there is a special assignment operator used to propagate signals
(<=). The statement wait on X, Y; suspends the logic process until at least one of
the signals, X or Y, is changed. Next we declare the design entity Full_Adder and
its port map. A structural style is used in the architectural body for the full-adder.
The description is in terms of the previously defined components.

EXAMPLE 1.3

Box 1.3 shows the VHDL code for a test bench for testing the full-adder described
in Example 1.2.

- ENTITY DECLAEATION
entity Test_gen is
port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);
end Test_gen;
-- ARCHITECTURAL BODY
architecture Behavior_desc of Test_gen is
begin
A <= '!', '0' after 20 ns, '0' after 40 ns, '0' after 60 ns, '0' after 80 ns, '!' after
100 ns,
'!', after 120 ns,'!' after 140 ns,'!' after 160 ns, '0' after 180 ns ;
B <= '!', '0' after 20 ns, '0' after 40 ns, '!' after 60 ns, '!' after 80 ns, '0' after
100 ns,
'0', after 120 ns,'!' after 140 ns,'!' after 160 ns, '0' after 180 ns ;
Carry_in <= '!', '0' after 20 ns,'!' after 40 ns, '0' after 60 ns,'!' after 80 ns,
'0' after 100 ns,'!' after 120 ns, '0' after 140 ns,'!' after 160 ns,
'0' after 180 ns ;
end Behavior_desc;

~ Dummy entity for the test bench
entity Testjbench is
end Test_bench;

- ARCHITECTURAL BODY
architecture Behavior_desc of Testjbench is
signal x, y, z, u, v: Bit;
component Generator
port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);
end component;
component Adder
port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);
end component;

for SQ: Generator use entity Test_gen(Behavior_desc);
for Si: Adder use entity Full_Adder(Behavior_desc);