Page 521 - DSP Integrated Circuits

506 Chapter 11 Processing Elements

EXAMPLE 11.12
Show that a second-order section in direct form
I can be implemented by using only a single PE
based on distributed arithmetic. Also show that
the PE can be pipelined.
In Figure 11.40 a set of D flip-flops has
been placed between the ROM and the shift-
accumulator to allow the two operations to over-
lap in time—i.e., the two operations are pipe-
lined. The number of words in the ROM is only
5
2 = 32.

Figure 11.40 Direct form I
implemented with
distributed
arithmetic

EXAMPLE 11.13
Suggest a scheme to implement a linear-phase FIR structure using distributed
arithmetic. Assume that N is even.
Figure 11.41 shows an implementation of an eleventh-order linear-phase FIR
filter. AT/2 bit-serial adders (subtractors) are used to sum the symmetrically placed
values in the delay line. This reduces the number of terms in the inner product.
Only 64 words are required whereas 2^ = 4096 words are required for a nonlin-
ear-phase FIR filter. For higher-order FIR filters the reduction in the number of
terms by 50% is essential. Further, the logic circuitry has been pipelined by intro-
ducing D flip-flops between the adders (subtractors) and the ROM, and between
the ROM and the shift-accumulator.
The number of words in the ROM is 2^ where N is the number of terms in the
inner product. The chip area for the ROM is small for inner products with up to
five to six terms. The basic approach is useful for up to 10 to 11 terms. However,
inner products containing many terms can be partitioned into a number of smaller
inner products which can be computed and summed by using either distributed
arithmetic or an adder tree. A complete inner product PE and several similar
types of PEs (for example, adaptors and butterflies) can be based on distributed
arithmetic. The main parts of an inner product PE are the shift-accumulator, the
coefficient ROM with decoder, and the control circuits. Overflow and quantization
circuitry are also necessary, but it is often advantageous to move parts of this cir-
cuitry to the serial/parallell converters used in the interconnection network, as
discussed in Chapter 8.