Page 147 - Engineering Digital Design

118 CHAPTER 3/BACKGROUND FOR DIGITAL DESIGN

FIGURE 3.40
Logic circuit for the function given in Example 3.4.

EXAMPLE 3.4 Use three NAND gates and two EQV gates (nothing else) to implement the
following function exactly as written:

F(H) = [(W © Y) 0 (XZ) + WY](H)

The solution is shown in Fig. 3.40.

EXAMPLE 3.5 A simple function of three inputs is given by the following expression:

(a) Construct the logic circuit by using AND/NOR/INV logic. Assume that the
inputs arrive active high.
(b) Construct the CMOS circuit for the function given in Part (a).
(c) Obtain the physical truth table for the circuit of Part (b).
(d) Obtain the positive logic truth table for the circuit of Part (b).

The solutions to Example 3.5 are given in Fig. 3.41. Notice that PMOS and NMOS are
organized according to Fig. 3.5, and that the PMOS section generates the complement of
that of the NMOS section, hence the complementary MOS. Also note that the output of the
A inverter is connected to both the PMOS and NMOS inputs of the complementary sections
forF.
EXAMPLE 3.6 Use the laws of Boolean algebra, including XOR algebra and corollaries, to
reduce each of the following expressions to their simplest form. Name the law(s) in each step.

[1] A + ABC + (B + C) = A + ABC + BC DeMorgan's law [Eqs. (3.15)]
= A + BC + BC Absorptive law [Eqs. (3.13)]
- A + B(C + C) Factoring law [Eqs. (3.12)]
= A + B AND and Or laws [Eqs. (3.7) and (3.8)]

[2] (a + b}(a + c)(a + c) = (a + b)(a + c • c) Distributive law [Eqs. (3.12)]
= (a + b)a AND and OR laws [Eqs. (3.7) and (3.8)]
= aa + ab Factoring law [Eqs. (3.12)]
= ab AND and OR laws