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400                     CHAPTER 9 / PROPAGATION DELAY AND TIMING DEFECTS


                    Fig. 9.7). The signal must propagate through each path until both paths reach a single gate,
                    called the hazard gate. If, for example, the signal requires more time to propagate through
                    Path 1 than through Path 2, the signal from Path 2 will reach the hazard gate before the
                    signal from Path 1. This asymmetry in path delay may cause a static hazard, depending on
                    the nature of the hazard gate and the gates in the two paths. Here, an inverter is considered to
                    be a gate and the hazard gate may or may not be the output gate. Also, lead delays are treated
                    as ideal with negligible path delay, and each gate has an inherent delay associated with it
                    that depends on its type, the number of inputs, and the technology used to implement it.
                       Static hazard analysis in multilevel functions is more complicated than in two-level logic.
                    Nevertheless, the static hazard is formed in agreement with the requirements of Fig. 9.7.
                    Each path may consist of any number of gates, and the gates in Path 1 may differ in several
                    respects from those in Path 2. Thus, if

                                         (S Path 1 delays) ^ (E Path 2 delays),         (9.8)


                    hazard formation is possible according to Fig. 9.7. Furthermore, in multilevel functions of
                    the type considered in this section, the difference between the Path 1 and Path 2 delays may
                    range from that of an inverter to one or more gate delays. Thus, the size (or strength) of
                    the static hazard glitch in a multilevel logic circuit may be considerable. Whereas the static
                    hazard glitch in two-level logic caused by an inverter may or may not cross the switching
                    threshold, a static hazard glitch in a multilevel XOR-type circuit may be quite large and
                    may easily cross the switching threshold.



                    9.3.1  XOP and EOS Functions
                    The simplest XOR/SOP or EQV/POS functions that produce static hazards are very similar
                    to conventional two-level functions. If no more than one term in an SOP function can be
                    active at any given time, the terms are mutually disjoint and the OR operators can be replaced
                    with XOR operators as indicated by Corollary I in Subsection 3.11.1. The result is an XOP
                    function. Hazards in an XOP function can be detected and eliminated by a method parallel
                    to that described for SOP functions in Section 9.2.
                       As an example, consider the reduced function N in SOP and XOP form:

                                                                                        (9.9)

                                        NXOP=ABC@ABD@ABCD®ABCD.                        (9.10)


                    The p-terms are mutually disjoint, so the direct conversion from SOP to XOP is permitted.
                    It follows from the conventional methods discussed in Section 9.2_that two static hazards
                    will occur in N$OP of Eq. (9.9): between coupled terms ABD and ABC onallll->0111
                    transition following a 1 — >• 0 change in A, and between coupled terms ABD and A BCD
                    ona(llll — > 1011) transition following a 1 -> 0 change in B. Each hazard is caused by
                    an inverter through which the coupled variable must pass. This inverter makes the two path
                    delays (Fig. 9.7) unequal, allowing the hazards to form following a change in each coupled
                    variable. Each hazard is eliminated by adding a consensus p-term consisting of the ANDed
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