Page 137 - Hardware Implementation of Finite-Field Arithmetic

120 Cha pte r F i v e

In a similar way, a parallel subtractor, in Z [x]/f(x) requires m Z
p p
subtractors, and its critical path delay is one Z subtractor. For the
p
subtraction given in Algorithm 5.4, where the function mod_m_
subtraction that implements the optimized binary mod p subtraction
presented in Algorithm 3.4 is used, the delay is given in Eq. (3.4).
Additionally, a VHDL file adder_subt_polynom.vhd modeling an
adder/subtractor is available at www.arithmetic-circuits.org. This
model includes the component adder_subtractor (described in Chap. 3)
with the following entity declaration:

entity adder_subtractor is
port (
x, y: in std_logic_vector(K-1 downto 0);
add_sub: in std_logic;
z: out std_logic_vector(K-1 downto 0)
);
end adder_subtractor;
The VHDL architecture is the following:

long_x <= ‘0’ & x;
xor_gates1: for i in 0 to K-1 generate
xor_y(i) <= y(i) xor add_sub;
end generate;
xor_y(K) <= ‘0’;
sum1 <= add_sub + long_x + xor_y;
c1 <= sum1(K);
z1 <= sum1(K-1 downto 0);
long_z1 <= ‘0’&z1;
xor_gates2: for i in 0 to K-1 generate
xor_p(i) <= P(i) xor not(add_sub);
end generate;
xor_p(K) <= ‘0’;
sum2 <= not(add_sub) + long_z1 + xor_p;
c2 <= sum2(K);
z2 <= sum2(K-1 downto 0);
sel <= (not(add_sub) and (c1 or c2)) or (add_sub and
not(c1));
with sel select z <= z1 when ‘0’, z2 when others;

Using the above component, the entity declaration of the adder/
subtractor of polynomials mod p is as follows:
entity add_sub_polynom is
port(
a, b: in polynomial;
add_sub: in std_logic;
z: out polynomial
);
end add_sub_polynom;
The VHDL architecture with the instantiation of the adder_subtractor
component is the following: