Page 282 - Hardware Implementation of Finite-Field Arithmetic

262 Cha pte r Ei g h t

entity NB_T1_multiplier is
port (
a, b: in std_logic_vector(M-1 downto 0);
c: out std_logic_vector(M-1 downto 0)
);
end NB_T1_multiplier;
The VHDL architecture follows:

yij_process: process(a,b)
variable yij: yij_array;
begin
for i in 0 to m-1 loop
for j in 1 to v loop
yij(i)(j):=(a(i) xor a((i+j) mod m))and(b(i)xor
b((i+j) mod m));
end loop;
end loop;
yij_s <= yij;
end process;
yiv_process: process(a,b)
variable yiv: yiv_array;
begin
for i in 0 to v-1 loop
yiv(i) := (a(i) xor a((v+i) mod m)) and (b(i) xor
b((v+i) mod m));
end loop;
yiv_s <= yiv;
end process;
c_s_process: process(a,b)
variable caux: std_logic_vector(M-1 downto 0);
begin
for i in 0 to m-1 loop
caux(i) := a(i) and b(i);
end loop;
c_s <= caux;
end process;
P1: process(yiv_s, yij_s, c_s)
variable f: std_logic;
variable r,r2,c_v: std_logic_vector(M-1 downto 0);
begin
f := yiv_s(0);
c_v := c_s;
for j in 1 to v-1 loop
for i in 0 to m-1 loop
r(i) := yij_s(i)(j);
end loop;
for i in 1 to k(j) loop
-- Squaring
r2(0) := r(m-1);
for i in 1 to m-1 loop
r2(i) := r(i-1);
end loop;
r := r2;