Page 285 - Hardware Implementation of Finite-Field Arithmetic
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Operations over GF (2 )—Normal Bases 265
8.7.1 Multiplier
The circuits are fully combinational. The cost and delay of several
multipliers are shown in Table 8.1.
Total
m LUTs Slices time
4 12 6 4
5 25 13 5
13 195 101 5
17 413 213 5
23 459 237 5
29 725 374 5
163 ∞
∞ means that the circuit does not fit within the device.
TABLE 8.1 Cost and Delay of Multiplication
8.7.2 Exponentiation
The circuits given in Table 8.2 are sequential implementations.
m FFs LUTs Slices Period
4 17 33 17 3.5
5 20 43 22 3.5
13 45 232 117 5.9
17 58 459 233 6.8
23 122 519 309 7.6
29 204 796 506 8.9
163 ∞
∞ means that the circuit does not fit within the device.
TABLE 8.2 Cost and Delay of Exponentiation
