Page 349 - Introduction to Microcontrollers Architecture, Programming, and Interfacing of The Motorola 68HC12

326 Chapter 11 Input/ Output

The counter/timer device is very flexible, and so it has many control bits that can be
set or cleared to permit it to implement different functions. In this section, we use just
one of these functions, to detect an edge of an input signal. Bits that we set or clear are
shown in clear rectangles in Figure 11.7 and discussed below; unused bits are shown in
rectangles with diagonal lines in them. We therefore merely initialize some control ports
in a "fixed" way and do not discuss the other ports in this counter/timer device.
The counter/timer device is enabled when TEN, bit 7 of TSCR, is T (J), We
illustrate our techniques using PORTT bit 0 (pin 105 in the 'A4, or pin 7 in the *B32),
Bits 1 and 0 of TCTLE determine which edges will be sensed; if that port's bit I is set,
then a falling edge on PORTT bit 0 sets the flip-flop; if its bit 0 is set, a rising edge sets
the flip-flop; and if both bits are set, either edge sets the flip-flop. Bit 0 of TFLG1 reads
this flip-flop. This bit can be tested in a gadfly loop, or if bit 0 of TMSKl is also set, it
causes an interrupt vectored through OxFFEE and OxFFEF. Bit 0 of TFLGI must be
cleared before it can be set sensed again; it is cleared by writing a T (1) into it.
For each bit position, PORTT can be used as a parallel I/O port whose direction is
specified by the corresponding bit in DDRT. Even when a PORTT bit is used to detect an
edge, the port can also be an input port to directly read the pin's signal.

11.5 Gadfly Synchronization
In the gadfly synchronization technique, the program continually "asks" one or more
devices what they are doing (such as by continually testing the timer flag bit). This
technique is named after the great philosopher, Socrates, who, in the Socratic method of
teaching, kept asking the same question until he got the answer he wanted. Socrates was
called the "gadfly of Athens" because he kept pestering the local politicians like a pesky
little fly until they gave him the answer he wanted (regrettably, they also gave him some
poison to drink). This bothering is usually implemented in a loop, called a gadfly loop,
in which the microcomputer continually inputs the device state of one or more I/O
systems until it detects DONE or an error condition in one of the systems. Gadfly
synchronization is often called polled synchronization. However, polling means
sampling different people with the same question—not bothering the same person with
the same question. Polling is used in interrupt handlers discussed in the next section; in
this text, we distinguish between a polling sequence and a gadfly loop.
A gadfly loop is illustrated by the flow charts shown in Figure 11.6b. The processor
keeps testing a status port, which is set by the device when it is done with the request
for the input, after which data can be read from the input port.
Gadfly synchronization generally requires more extensive initialization before the
device can be used. The counter/timer control registers must be set up so that when data
are to be output, a falling edge on PORTT bit 0 can set a flag bit. Bit 7 of the TSCR
needs to be set to enable any operation in the counter/timer. Bits 1 and 0 of TCTLE must
be set to 1 and 0 respectively, to indicate that a falling edge sets the TFLGI bit 0. This
flag can accidentally become set before the first output operation occurs, so to clear it
just in case it is set, $01 should be written into the TFLGI port. The initialization of the
counter/timer consists of the C statements: TSCR = 0x80; TCTLE = 2; TFLGI = 1,*.
It is optimally compiled to assembly language as: