Page 352 - Introduction to Microcontrollers Architecture, Programming, and Interfacing of The Motorola 68HC12

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The gadfly loop waits until a hardware-generated edge occurs, while the delay loop
waits a prescribed number of instruction executions. In general, delay loops do not
require as much hardware as gadfly loops, because a gadfly loop needs a status bit In
hardware and a means to set it. However, gadfly synchonization can wait exactly as long
as an I/O device needs, when hardware causes the edge to occur, while a delay loop is
generally timed to provide a delay that is the worst-case delay needed for the device,

11.6 Interrupt Synchronization

In this section, we consider interrupt hardware and software. Interrupt software can be
tricky, so some companies actually have a policy never to use interrupts but instead to
use the gadfly technique. At the other extreme, some designers use interrupts just because
they are readily available in microcomputers like 6812 systems. We recommend using
interrupts when necessary, but using simpler techniques whenever possible.
The hardware or I/O interrupt is an architectural feature that is very important to
I/O interfacing. Basically, it is invoked when an I/O device needs service, either to move
some more data into or out of the device or to detect an error condition. Handling an
interrupt stops the program that is running, causes another program to be executed to
service the interrupt, and then resumes the main program exactly where it left off. The
program that services the interrupt (called an interrupt handler or device handler) is very
much like a subroutine, and an interrupt can be thought of as an I/O device tricking the
computer into executing a subroutine. An ordinary subroutine called from an interrupt
handler is called an interrupt service routine. However, a handler or an interrupt service
routine should not disturb the current program in any way. The interrupted program
should get the same result no matter when the interrupt occurs.
I/O devices may request an interrupt in any memory cycle. However, the data
operator usually has bits and pieces of information scattered around and is not prepared to
stop the current instruction. Therefore, interrupts are always recognized at the end of the
current instruction, when all the data are organized into accumulators and other registers
(the machine state) that can be safely saved and restored. The time from when an I/O
device requests an interrupt until data that it wants moved is moved, or the error
condition is reported or fixed, is called the latency time. Fast I/O devices require low
latency interrupt service. The lowest latency that can be guaranteed is limited to the
duration of the longest instruction, because the I/O device could request an interrupt at
the beginning of such an instruction's execution.
The condition code register, accumulators, program counter, and other registers in
the controller and data operator, the machine state, and these nine bytes are saved and
restored whenever an interrupt occurs. After completion of a handler, the last instruction
executed is return from interrupt (R.TI). It pulls the top nine bytes from the stack,
replacing them in the registers the interrupt took them from.
Interrupt techniques can be used to let the I/O system interrupt the processor when it
is DONE, so the processor can be doing useful work until it is interrupted. We first
look at steps in an interrupt. Then we consider interrupt handlers and the accommodation
of critical sections.