Page 282 - System on Package_ Miniaturization of the Entire System
P. 282
256 Cha pte r F o u r
68. J. Mao, J. Srinivasan, J. Choi, M. Swaminathan, and N. Do, “Modeling of field pen-
etration through planes in multilayered packages,” IEEE Transactions on Advanced
Packaging, vol. 24, no. 3, August 2001, pp. 326–333.
69. R. Ito and R. W. Jackson, “Parallel plate slot coupler modeling using two dimen-
sional frequency domain transmission line matrix method,” Proc. IEEE EPEP,
2004, pp. 41–44.
70. J. Lee, M. D. Rotaru, M. K. Iyer, H. Kim, and J. Kim, “Analysis and suppression
of SSN noise coupling between power/ground plane cavities through cutouts
in multilayer packages and PCBs,” IEEE Transactions on Advanced Packaging,
vol. 28, no. 2, May 2005, pp. 298–309.
71. SungJun Chun, “Methodologies for Modeling Simultaneous Switching Noise in Multi-
layered Packages and Boards,” PhD Dissertation, Georgia Institute of Technology,
April 2002.
72. Larry Smith, Raymond Anderson, Doug Forehand, Tom Pelc, and Tanmoy Roy,
“Power distribution system design methodology and capacitor selection for
modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22,
no. 3, August 1999, pp. 284–291.
73. Bernd Garben, George A. Katopis, and Wiren D. Becker, “Package and chip
design optimization for mid-frequency power distribution decoupling,” Electrical
Performance of Electronic Packaging, 2002, pp. 245–248.
74. Om P. Mandhana and Jin Zhao, “Comparative study on the effectiveness of on-
chip, on package and PCB decoupling for core noise reduction by using broad-
band power delivery network models,” Electronic Components and Technology
Conference, 2005, pp. 732–739.
75. Nanju Na, Timothy Budell, Charles Chiu, Eric Tremble, and Ivan Wemple,
“The effects of on-chip and package decoupling capacitors and an efficient ASIC
decoupling methodology,” Electronic Components and Technology Conference, 2004,
pp. 556–567.
76. Tawfik Rahal-Arabi, Greg Taylor, Matthew Ma, Jeff Jones, and Clair Webb,
“Design and validation of the core and I/O’s decoupling of the Pentium 3
R
and Pentium 4 Processors,” Electrical Performance of Electronic Packaging, 2002,
R
pp. 249–252.
77. Richard Ulrich, “Embedded resistors and capacitors for organic-based SOP,” IEEE
Transactions on Advanced Packaging, vol. 27, no. 2, May 2004, pp. 326–331.
78. Istvan Novak, “Lossy power distribution networks with thin dielectric layers
and/or thin conductive layers,” IEEE Transactions on Advanced Packaging, vol. 23,
no. 3, August 2000, pp. 353–360.
79. Hyungsoo Kim, Byung Kook Sun, and Joungho Kim, “Suppresion of GHz range
power/ground inductive and simultaneous switching noise using embedded
film capacitors in multilayer packages and PCBs,” IEEE Microwave and Wireless
Components Letters, vol. 14, no. 2, February 2004, pp. 71–73.
80. K. Y. Chen, William D. Brown, Leonard W. Schaper, Simon S. Ang, and Hameed
A. Naseem, “A study of high frequency performance of thin film capacitors for
electronic packaging,” IEEE Transactions on Advanced Packaging, vol. 23, no. 2, May
2000, pp. 293–302.
81. Joel S. Peiffer, William Balliette, and 3M Company, “Decoupling of high speed
digital electronics with embedded capacitance,” 38th International Symposium on
Microelectronics, September 2005.