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Integrated Chip-to-Chip Optoelectr onic SOP   331


                    In the remainder of this chapter we will consider the development of digital-optical
                    SOP technology as it applies to high-performance computing, servers, and routers.


               6.4  Advantages of Optoelectronic SOP


                    6.4.1  Comparison of High-Speed Electrical and Optical Wiring Performance
                    There are three forces that drive SOP technology for computing, namely, (1) performance,
                    (2) power, and (3) cost. These translate into seven technology improvements that are
                    made possible by introducing optoelectronics architecture into digital systems. These
                    improvements are (1) nearly invariant (bandwidth × distance) product over the entire
                    network, (2) interconnect density that is far greater than copper densities, (3) negligible
                    crosstalk and insensitivity to simultaneous switching noise (SSN), (4) three-dimensional
                    optical wiring, (5) direct, high-speed processor-to-processor optical links that lead to
                    architectural simplicity by reducing the use of much slower copper bus lines, number
                    of printed circuit board (PCB) layers and vias, and capacitors, (6) greatly reduced node
                    crossing delays in multiprocessor networks by direct optical wiring and long-reach off-
                    chip synchronization, and (7) minimum number of components used for noise
                    suppression [15].
                       It is well known that the bandwidth of copper interconnects is intrinsically limited
                    by numerous factors such as skin effect, inductance, capacitance, and EM radiation, as
                    well as extrinsic factors such as the dielectric susceptibility of the insulator which may
                    cause frequency dispersion and signal attenuation, crosstalk, and power supply noise.
                    The intrinsic limitation of the (bandwidth × distance) product for unequalized copper
                    lines is summarized in Equation (6.1), where B max  is the maximum bandwidth capacity,
                    A is the cross-sectional area of the copper line, and l is its length [16].

                                              B   ≤  . 24 x10 7  A/ρ Gb/s                (6.1)
                                               max
                    A graphical representation of Equation (6.1), namely the dependence of the bandwidth of
                    two unequalized copper transmission lines on cross-sectional area and distance, is shown
                    in Figure 6.4 and compared with the bandwidth for a multimode (MM) polymer waveguide
                    carrying a single wavelength (1310 nm) with an attenuation coefficient of –0.2 dB/cm.
                       In comparison, a single, long-distance optical fiber carrying 100 colors, each having
                    a 10-Gb/s capacity, has an aggregate bandwidth of 1 Tb/s. Under development are
                    100-Gb/s laser modulators and detectors with similar speed to support the Ethernet
                    infrastructure [2]. The ability to move massive quantities of data at several Tb/s over
                    long distances makes it possible to contemplate real-time distributed, task-specific,
                    parallel computing. Realizing the potential advantages of an optical network architecture
                    that links multiple nodes (processors, memory banks, I/O buffers), a number of authors
                    have simulated a variety of optical bus designs and data passing protocols in symmetric
                    multiprocessing (SMP) and massively parallel processing (MPP) machines. In SMP
                    (servers), all processors share the same memory via one or more buses, and each CPU
                    takes on the next available task. In MPP (supercomputers), problem segments are solved
                    in locked step. Each CPU contains its own copy of the operating system and application
                    and has access to its own memory. Tasks are assigned to each CPU, and communication
                    between MPP subsystems takes place via high-speed interconnects where the optics
                    solution can play a role.
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