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34    Cha pte r  O n e



               1.11 Summary
                    SOP is about system miniaturization enabled by IC and system integration by ultrathin-
                    film components at microscale in the short term and nanoscale in the long term for all
                    system components. Some of these thin-film system technologies that SOP enables can
                    be used in CMOS ICs as overlays, as thin films on top of silicon wafers (TFOS) and
                    silicon carriers, or on ceramic and glass substrates or embedded into multilayer ceramic
                    or organic laminate packages and boards.
                       SIP is defined in this book as the stacking of ICs and packages. But since SIP is also
                    often referred to as a total system technology that miniaturizes and integrates all system
                    components such as passives, actives, thermal structures, power sources, and I/Os, if this
                    happens, then SOP and SIP are identical. But so far, this has not been demonstrated.



               Acknowledgments
                    The authors gratefully thank the Georgia Tech PRC team of faculty, engineers, students,
                    and industry advisors for their contributions in the development of the SOP technology.
                    The authors also thank both the Georgia Research Alliance and the National Science
                    Foundation Engineering Research Centers for their funding of SOP technology for more
                    than a decade.



               References
                      1. R. R. Tummala et al.,  Ceramic Packaging Technology, Microelectronics Packaging
                        Handbook. New York: Van Nostrand, 1988.
                      2. Y. Yano, T. Sugiyama, S. Ishihara, Y. Fukui, H. Juso, K. Miyata, Y. Sota, and K. Fhjita,
                        “Three dimensional very thin stacked packaging technology for SiP,” in Proc. 52nd
                        Electronic Components and Technology Conference, 2002.
                      3. K. Lim, M. F. Davis, M. Maeng, S. Pinel, L. Wan, L. Laskar, V. Sundaram, G. White,
                        M. Swaminathan, and R. Tummala, “Intelligent network communicator: Highly
                        integrated system-on-package (SOP) testbed for RF/digital/opto applications,” in
                        Proc. 2003 ElectronicComponents and Technology Conference, pp. 27–30.
                      4. R. Tummala, “SOP: Microelectronic systems packaging technology for the 21st cen-
                        tury, ” Adv. Microelectron., vol. 26, no. 3, May–June 1999,  pp. 29–37.
                      5. R. Tummala, G. White, V. Sundaram, and S. Bhattacharya, “SOP: The microelectron-
                        ics for the 21st century with integral passive integration,” Adv. Microelectron., vol. 27,
                        2000, pp. 13–19.
                      6. R. Tummala and V. Madisetti, “System on chip or system on package,” IEEE Design
                        Test Comput., vol. 16, no. 2, Apr. –June 1999, pp. 48–56.
                      7. R. Tummala and J. Laskar, “Gigabit wireless: System-on-a-package technology, ”
                        Proc. IEEE, vol. 92, Feb. 2004, pp. 376–387.
                      8. ITRS 2006 Update
                      9. H. K. Kwon et al., “SIP solution for high-end multimedia cellular phone,” in IMAPS
                        Conf. Proc., 2003, pp. 165–169.
                     10. S. S. Stoukatch et al., “Miniaturization using 3-D stack structure for sip application,”
                        in SMTA Proc., 2003, pp. 613–620.
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