Page 379 - Sami Franssila Introduction to Microfabrication

358 Introduction to Microfabrication

CT/PT even further: in the backend of the process the for example, oxygen precipitation and wafer curva-
lot is made smaller; for instance, only three wafers will ture. Re-claim wafers are cheaper choices for non-
be processed to completion and CT/PT can be as low critical tests: as thin-film thickness monitors, as equip-
as 0.5. There can be only a limited number of hot lots ment qualification wafers or as regular particle-test
running simultaneously because they disturb the normal wafers.
fab operations.
Yields of hot lots tend to be consistently better than
those of standard lots. This can be explained by a simple 37.4 COST-OF-OWNERSHIP (CoO)
particle deposition model: hot lots spend less time in the
wafer fab, and there is less time available for particles Difficulties in tool performance assessment have led
to deposit on the wafers. to the introduction of a new figure-of-merit, the cost-
Split lots, which have process variations designed in of-ownership, CoO, which tries to put all tools on
them (e.g., wafers having different implant doses but equal footing, calculated over the lifetime of the tool.
otherwise identical processing), carry a wealth of infor- Equipment capital investment has very little meaning in
mation, but at the enormous cost of experimentation. IC cost calculations if other major factors such as yield
In split lot experiments, it is important to understand
and throughput are neglected. CoO is an estimate of all
which process steps are single-wafer and which are costs associated with a certain piece of equipment, and
batch, because running split lots in batch processes is it can be used to compare different mixes of fixed and
time-consuming. running costs. Yield, or alternatively cost per good chip,
Regular wafers are run in lots of 25 or 50 wafers. is of paramount importance, and therefore CoO-models
For batch processes such as oxidation, many batches are are rather ‘personal’: equipment maintenance, process
combined, which leads to higher CT/PT. Sometimes, a specification tightness/looseness, the number of monitor
lot is made up of 24 wafers plus a monitor wafer. The wafers, all affect the yield, and the yield has often the
monitor wafer is not physically one and the same wafer
biggest contribution to CoO.
but an allocation only: in gate oxidation, it is a prime
wafer that then continues to polysilicon deposition, poly
doping and polysilicon etching, and exits after that. A Cost/wafer = (tool cost/throughput) + process cost
new monitor wafer starts at first inter-level dielectric (37.1)
deposition, and is then used as a contact hole etch Process cost includes chemicals, targets, water,
monitor and as first metal resistance and step coverage labour, electricity, administration, and so on. Wafer cost
monitor. This monitor is not a prime wafer, but a can be added, or treated separately. Cost-of-ownership
monitor-quality wafer. (CoO) is defined as
In addition to device and process-specific monitor
equipment + labour + consumables + operation
wafers that run with the product wafers, a lot of other + yield loss
monitor wafers run in a wafer fab. These are used for CoO =
equipment life × throughput × utilization
× rework rate
• equipment qualification, for example, after mainte- (37.2)
nance; The following calculation (from Moritz, H.: Profes-
• regular monitoring, for example, particle tests, film sional i-line Lithography, Lecture Notes, IBM, 1993)
thickness/uniformity; shows how different components relate to lithography
• process development, for example, modifying an cost.
existing process step;
• short loop test wafers, for example, via-chain test.
Equipment cost $3 500 000
In the start-up phase of a new fab, product Equipment life 5 years
wafers may in fact represent less than half of all Utilization 85%
the wafers. Test/monitor wafers are often re-claim Throughput 25 wafers/hour
wafers. Reclaim wafers are wafers that have been Rework rate 0.90 (= 10% of wafers reworked)
“reconditioned” after processing. Thin films have been
etched away, and the wafers may have been re-
polished and inspected. Re-claim wafers have been This translates to 826 000 wafers processed during
through various process steps, especially thermal pro- equipment lifetime, or investment cost of $4.7 for a
cesses, which affect the properties of the wafer bulk, lithography step. Process cost is estimated as follows: