Page 378 - Sami Franssila Introduction to Microfabrication

Wafer Fab 357

that hard disk drive memory density increases faster than one mask is product-specific, and all the other masks
semiconductor memory density. are shared between many products. Of course, semi-
custom chips cannot use silicon area very efficiently,
but the cost reduction relative to full custom design is
37.2 MANUFACTURING CHALLENGES significant.
The IC industry is faced with a number of challenging
issues in fab economics, device structures and pack- 37.3 CYCLE TIME
aging. Fab cost is not only high, but the amortization
times are also very short, five to seven years only. Cycle time (CT) is the number of days it takes to
Lithography cost, especially, is rising very fast, with complete a lot. Process time (PT) is the actual time
20- to 30-million-dollar pricetags for lithography tools it takes for the wafer to be processed. Process time
in sight. Wafer size transition from 200 to 300 mm intro- is the total time when processes act on the wafers,
duces additional costs because all tooling has to be while cycle time includes idle time, like queuing.
upgraded, not just process tools but metrology and test The ratio of cycle time to process time, CT/PT, is
tools as well. Most of the 300 mm tools for the 0.13 µm a measure of fab efficiency. For standard processing,
generation can later be upgraded for the 90 nm gen- CT/PT is about 2; wafers spend half the time in queue
eration, and a few are going to be useful even in the and storage.
65 nm generation. In 2003, there were 30 fabs running Cycle time and process time are intimately coupled
300 mm wafers. to batch versus single-wafer tool combination in a
With 100 million transistors on a 0.13 µm logic chip fab. Most front-end processes are batch, and most
(which translates to some 20 to 30 million devices per backend processes, single-wafer. For batch processes,
square centimetre), design complexity is enormous, and process time is ‘overhead + batch time’, which is fairly
the same applies to device testing. CMOS was orig- constant; but for single-wafer processes process time is
inally a solution to power consumption: CMOS logic ‘overhead + lot size × single-wafer time’, and lot size
consumes energy only during switching, but the sheer has a major effect. All-single-wafer fabs have been
number of devices means that excessive amounts of experimented with, and record cycle times of three
waste heat are generated in advanced chips. Chip cool- days have been demonstrated for 0.25 µm CMOS. There
ing has two elements: hot spot cooling and overall are no single-wafer fabs running volume production,
cooling. Power consumption of 100 W is becoming but in order to reduce risks associated with billion-
typical in high-performance processors (power densi- dollar fabs, the minifab concept has been created.
2
ties 30 W/cm ), whereas processors for battery-powered Minifabs are low-volume fabs with mostly single-
devices consume only a fraction of a watt. Connec- wafer and some small-batch equipment (batch size
tions from the chip to the outside world require some of 25 wafers in thermal processes, versus 200 wafer
advanced solutions: attaching lead to just chip periphery batches in high volume fabs). Such minifabs are
is not enough when 1000 connections need to be made. expected to be more agile because the cycle times will
Various ball grid and bump-metallization schemes have be shorter, and production scheduling is going to be
been introduced. In these approaches, the traditional more flexible. There will be little equipment duplication,
division of labour between wafer fab and the packaging and only some dedicated equipment for certain process
house is shifting; a packaging house can do wafer pro- steps. One thermal processor might be running various
cessing – lithography, electrodeposition of bump metal processes, maybe with only front-end versus backend
and bump anneal – before the usual steps of testing, dic- separation, which is for keeping metallic contamination
ing and assembly. at bay.
Because photomask cost is rapidly rising, it is Other ways to reduce cycle time include lot status
becoming increasingly difficult to make small series and priority classification schemes. Hot lots (aka rush
production. A photomask set for advanced CMOS can lots) are priority lots that receive preferential treatment
cost $500 000, and if a wafer sells for $10 000, anything in the fab. When a hot lot arrives at a process tool, it
below 50 wafers does not cover even the non-recurring is processed in front of the queue. Hot-lot cycle time
starting costs. Semi-custom chips solve this problem, at may be 30% less than that of a regular lot. ‘Super hot’
least partially: front-end processing, and therefore the lots (aka bullet lots) are even more prioritized: process
transistors, is identical in all products, and chips are equipment is reserved for the super-hot lot so that it
customized by a few customer-specific photomasking can be processed as soon as it arrives. For a super-
steps later in the process. In the best case, only hot lot, CT/PT is thus 1, but there is a way to reduce