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7-6 MEMS: Design and Fabrication

decreased. The initial rise of the current is due to the rapid generation of electron-hole pairs (EHPs) dur-
ing the initial stages of the etching process. These carriers are available near the surface of the SiC to par-
ticipate in the chemical reaction process.
Acombination of various mechanisms leads to the gradual decay of the current, as shown in Figure 7.2.
As the etching progresses, the reacting species will need to diffuse through the porous SiC layer being
formed; thus, they can get to the bulk SiC surface just as the products of the reaction need to diffuse out.
Therefore, as the porous SiC thickness increases, the mass transport process is slowed down, resulting in
areduced rate of reaction. The porous SiC will also shade the bulk SiC from the UV intensity, resulting
in a drop in the EHPs needed to sustain the reaction.
Once the etching reaches the underlying p-type epilayer, the abrupt change in epilayer conductivity

from n -SiC to that of the underlying p-type SiC causes the etching to stop. Since most of the electric

field is confined within the n -SiC and the applied 1.7 V SCE anode potential causes the np-junction to be
reverse-biased, only an insignificant leakage current will flow through the p-epilayer and be transported
to participate in the etching process at the electrolyte interface.
The current–time curves are repeatable between two etching runs, as can also be seen in Figure 7.2. It

should be noted that the etch rates of the n -SiC epilayer is dependent on the UV intensity and the doping

level of the epilayer. By increasing the UV intensity, which causes more EHPs to be generated, the n -SiC
epilayer can be etched more rapidly and more selectively between n- and p-type, because fewer carriers
are present at the p-epilayer to participate in the etching.
SiC etch rates greater than 20nm/min have been achieved. The wafer is thermally oxidized and then
dipped in 49% HF to remove the porous layer that formed during anodization. After the process of selec-
tive etching, the np-junction is sometimes not well-isolated electrically, which leads to unsteady outputs

during device operation. To prevent this situation from occurring, the etching time of the n piezoresistor
epilayer is increased, so that the PECE process partially occurs in the p-epilayer. Poor electrical isolation
can also be avoided if the junction isolation is verified immediately after PECE before the mask is stripped.
Usually, a second thermal oxidation is carried out to ensure that the np-junction of all the devices is
well-isolated. The metal contact via is opened in the oxide by conventional photolithographic process and
buffered-HF wet etching to expose sections of the resistors. Subsequently, ohmic contact metallization is
deposited and patterned over the via to form the electrical contacts. This process is followed by the dep-
osition and patterning of the diffusion barrier to form the final device shown in the cross section of
Figure 7.3(a). The top view drawing of the sensor is shown in Figure 7.3(b).

Another process that can be used to pattern n -SiC epilayers is the ECE. As stated earlier, when the

small positive anodic potential is applied through the ohmic contact on the n -SiC, current cannot flow

between the n -SiC epilayer and the underlying p-SiC substrate. However, etching selectivity may not be
as high as in the PECE, since leakage current will increase for the voltage needed to perform a high etch-
ing rate with dark current.
After the platinum mask is removed, the surface of the underlying resistor is sometimes pitted. The pit-
ting is the result of the pinholes in the platinum, which allow electrolyte to seep through the mask and

etch the otherwise protected n -SiC surface. Therefore, it is important to ensure that the etch mask used
for the pattern transfer is free of pinholes.
Undercutting of the piezoresistors during etching may also occur as a result of the small dark current

between the edge of the etching n -SiC and the electrolyte under bias of the anodic potential. Although
this potential is made small enough to avoid reverse-bias current flow between the n-type epilayer and
the underlying p-type epilayer, lateral current conduction between the expanding side of the n-type SiC
epilayer and the electrolyte allows undercutting etching to proceed during the PECE process.
The above problems typically lead to undesirable nonuniformity in the resistor patterns. Using n-type
epilayers with lower doping reduces dark etching at anodization potentials of about 1.7 V SCE and can min-
imize these effects. This result is due to the fact that, at that anodic potential, fewer carriers from the dark
current are injected into the electrolyte relative to the EHPs generated by the UV light source. However,
this approach means the gauge factor and the temperature effects of the piezoresistor will change since
gauge factor is dependent on doping level.

© 2006 by Taylor & Francis Group, LLC