Page 78 - Mechatronic Systems Modelling and Simulation with HDLs

4.3 CHARACTERISATION OF HARDWARE DESCRIPTION LANGUAGES 67

addition of four numbers can be unambiguously described in terms of their function
as follows:

y = a + b + c + d; (4.1)

The order in which the expression is evaluated is unimportant here since the
commutative law for addition applies. However, if the addition is considered on
the structural level then the sequence can no longer be neglected. For example, the
following two alternatives exist:
y = (a + b) + (c + d); (4.2)

y = ((a + b) + c) + d; (4.3)

Corresponding realisations by adders are shown in Figure 4.2. It turns out that
the realisation of the expression shown on the left is completed more quickly than
that on the right since only two adding stages have to be run in this case.
Formulation on a behavioural level can thus significantly reduce the complexity
of a circuit description. Higher operations such as addition, subtraction, multi-
plication, represent a few hundreds or even a few thousands of gates. Thus the
readability of such a description is significantly greater than that of other circuit
descriptions. Furthermore, the reuse of descriptions that were originally developed
in a different context is made easier.
Finally, hardware description languages generally open up the option of con-
sidering the individual parts of a circuit in different abstractions, see Figure 4.3.
Thus circuits or systems can be fully simulated if each of their modules possesses
an abstract behavioural description. This initially offers an efficiency gain com-
pared to a complete simulation of the finished design. Furthermore, as time goes
on the individual blocks can be refined during the design process, until the design
has achieved the required level of abstraction for the individual parts. In particu-
lar, refinements by several circuit developers can be implemented independently

a b c d a b c d

q q
Figure 4.2 Two versions of an adder for four numbers