Page 81 - Mechatronic Systems Modelling and Simulation with HDLs

70 4 MODELLING IN HARDWARE DESCRIPTION LANGUAGES

an interface section (PACKAGE) and an implementation section (PACKAGE BODY).
A fifth group of descriptions specifies which architectures should form the basis
for a simulation. These are also called configurations (CONFIGURATION).

4.5.2 Structural and behaviour-oriented modelling

Structural modelling formulates the submodules from which a module is composed.
In contrast to this, behaviour-oriented modelling describes the function and timing
of the module. Let us clarify this using the example of a full adder. Hardware
description 4.1 shows the interface description of a fictitious full adder in VHDL.
Comments for the rest of the lines are preceded by a double minus sign. Using the
LIBRARY and USE instructions a PACKAGE is first referenced, which includes the
necessary types for the digital signals, e.g. std_logic.The ENTITY description
mainly consists of a PORT instruction, which declares the inputs and outputs of the
full adder.
LIBRARY IEEE;
-- IEEE Package for logic types
USE IEEE.std_logic_1164.all;

ENTITY full_adder IS
-- two sum inputs, one Carry-In
-- one sum output, one Carry-Out ...
PORT (i1, i2, ci: IN std_logic;
sum, co: OUT std_logic);
END full_adder;

Hardware description 4.1 Interface description of a full adder
The first possibility is represented by structural modelling, in which the full
adder is made up of a half adder and an Or gate, see Hardware description 4.2.
The timing is taken from the timing of the underlying modules.

ARCHITECTURE structure OF full_adder IS
...
BEGIN
...
inst1 : half_adder(i1 ,i2 ,tc1 ,ts1); -- Instantiation HA
inst2 : half_adder(cin ,ts1 ,tc2 ,sum); -- Instantiation HA
inst3 : or_gate (tc1 ,tc2 ,co); -- Instantiation OR
END structure;

Hardware description 4.2 Structural description of a full adder
The simplest form of behavioural modelling is the data flow description, in
which the underlying Boolean function is merely assembled from basic functions
and the calculation of the results performed after a delay. This is shown in Hardware
description 4.3.