Page 80 - Mechatronic Systems Modelling and Simulation with HDLs

4.5 MODELLING PARADIGMS 69

placement of orders. Thus all CAE providers were forced to support VHDL. Other
languages were also standardised such as, for example, Verilog-HDL, which was
initially designed as a proprietary language. The great advantage of such standards
is that they promote the exchange of circuit descriptions and furthermore make
it possible for the providers of CAE tools to exchange simulators, for example,
without the reformulation of the models into another language and the significant
costs associated with this. Since 1987 VHDL has been a standard for the devel-
opment of digital circuits and systems, which is being continuously improved and
expanded. A significant aspect of this is the expansion around analogue and mixed
3
analogue-digital constructs. In 1999 the IEEE standard 1076.1 (VHDL-AMS )was
passed, which covers the full language scope of VHDL and additional constructs
for the modelling of analogue processes. For an introduction to VHDL the reader
is referred to the books of Ashenden [15], Pellerin and Taylor [319] and Perry
[334]. With regard to VHDL-AMS, as yet there is only the provisional version of
the IEEE standard 1076.1 [160] and an associated tutorial [16].
As early as 1993 VHDL and Verilog-HDL enjoyed a clear predominance in the
digital field compared to other languages, see Carrol [61]. Today hardly any other
languages are used in the digital field. A similar concentration will presumably
also take place in the field of analogue hardware description languages.

4.5 Modelling Paradigms

4.5.1 Introduction

In the following, the most important techniques of digital and analogue mod-
elling in hardware description languages will be described. For example, the lan-
guage VHDL-AMS, which covers the most important constructs of other hardware
description languages, will be considered in this connection. The aim of the descrip-
tions that follow is to convey an impression of the modelling possibilities available
using hardware description languages. However, they are not a substitute for the
corresponding literature. In the following, the key words in hardware description
languages are written in upper case letters and all identifiers in lower case let-
ters. In principle this makes no difference, since in VHDL and VHDL-AMS, no
differentiation is made between upper and lower case.
A VHDL model is organised into various descriptions. Every module has pre-
cisely one interface description, which in principle specifies the corresponding
interface signals and their type and direction. Such a description is also called an
ENTITY. For each ENTITY there is one or more ARCHITECTURE descriptions that
contains the different variations of the modelling of the module. For example, in
the following section three architectures will be listed for a module. For frequently
used constructs it is possible to define packages, which are themselves split into

3 VHDL analogue and mixed signal extensions.