Page 114 - A Practical Guide from Design Planning to Manufacturing

Design Planning 87

determine the cost of an individual chip. The cost of processing a wafer does
not vary much with the number of die, so the smaller the die, the lesser
the cost per chip. The total number of die per wafer are estimated as: 6

π (wafer diameter/2) 2 π π × wafer diameter
Die per wafer = −
die area 2 × die area

The first term just divides the area of the wafer by the area of a single
die. The second term approximates the loss of rectangular die that do
not entirely fit on the edge of the round wafer. The 2003 International
Technology Roadmap for Semiconductors (ITRS) suggests a target die
2
2
size of 140 mm for a mainstream microprocessor and 310 mm for a
server product. On 200-mm wafers, the equation above predicts the
mainstream die would give 186 die per wafer whereas the server die size
2
would allow for only 76 die per wafer. The 310-mm die on 200-mm
wafer is shown in Fig. 3-7.

1 2 3 4
5 6 7 8 9 10

11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27 28

29 30 31 32 33 34 35 36 37 38

39 40 41 42 43 44 45 46 47 48

49 50 51 52 53 54 55 56 57 58

59 60 61 62 63 64 65 66

67 68 69 70 71 72

73 74 75 76

2
Figure 3-7 310-mm die on 200-mm wafer.
6
Hennessy et al., Computer Architecture, 19.